MC145572PB Freescale Semiconductor, MC145572PB Datasheet - Page 65

• Manufacturer Part Number: MC145572PB
• Manufacturer: Freescale Semiconductor

Specifications of MC145572PB

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Not Compliant

MOTOROLA
4.4.16
4.4.17
BR15: Revision Number Register
This read–only register contains the revision number of the particular U–interface transceiver device.
BR15 is accessed by a SCP or PCP transfer when BR7(b7) is 0 and the byte address is 15.
Mask 7:0
These bits allow for an electronic determination of the revision number of the MC145572 U–interface
transceiver manufacturing mask set.
BR15A: Baud Clock and Timing Test Register
This register is used to enable clock and test data outputs. All writable bits in this register are cleared
to 0 after a reset. BR15A is accessed by a CPI transfer when BR7(b7) is 1 and the byte address
in the SCP transfer is 15. The write–only bits in this register remain write–only bits when BR14(b6)
is set to 1.
FREQ ADAPT
This bit is a read/write bit. There is no effect on the operation of the U–interface transceiver unless
Control Steer (BR12 (b7)) is set to 1. When Control Steer is 1 and FREQ ADAPT is set to 1, the NT
frequency adaptation circuits are enabled to adjust the external crystal frequency. Setting this bit to
0 freezes the frequency adaptation circuits in their current state.
Jump Disable
This bit is a read/write bit. Setting this bit to 1 disables the digital PLL when Activation Control Steer
(BR12(b7)) is set to 1 (this bit is used for Motorola test purposes only).
Enable TxSFS
When set to 1 with BR14(b0) set to 1, this bit enables the transmit Superframe Sync to be output.
Enable Eye Data and Baud Clock
When set to 1, this bit enables the EYEDATA, SYSCLK, Rx BAUD CLK, and Tx BAUD CLK output
pins.
BR15A
BR15
When the MC145572 is configured for IDL2 and SCP operation the 15.36 CLKOUT,
4.096 CLKOUT, and BUFXTAL pins default to “on.” Software written for
MC145472 / MC14LC5472 that set BR15A (b1 or b2) is not affected when an existing
MC145472 or MC14LC5472 product is upgraded to MC145572.
ADAPT
Mask 7
FREQ
b7
b7
Freescale Semiconductor, Inc.
rw
ro
For More Information On This Product,
Reserved bits b5 and b4 must be set to 0 at all times.
Mask 6
Disable
Jump
b6
b6
Go to: www.freescale.com
rw
ro
Reserved
Mask 5
b5
b5
MC145572
rw
ro
Reserved
Reserved
CAUTION
Mask 4
NOTE
b4
b4
wo
ro
ro
Reserved
Mask 3
Enable
TxSFS
b3
b3
wo
ro
ro
Reserved
Reserved
Mask 2
b2
b2
wo
ro
ro
Reserved
Reserved
Mask 1
b1
b1
wo
ro
ro
Reserved
Eye Data
and Baud
Mask 0
Enable
Clock
b0
b0
wo
ro
ro
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