MC145572PB Freescale Semiconductor, MC145572PB Datasheet - Page 27

• Manufacturer Part Number: MC145572PB
• Manufacturer: Freescale Semiconductor

Specifications of MC145572PB

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Not Compliant

MOTOROLA
3.3.2
Mode Selection Pins
These inputs define the mode of operation for the MC145572. More information on the function of
the device in specific modes can be obtained from Chapter 5, MCU Mode Device Functionality and
Chapter 8, GCI Mode Functional Description .
V SS Rx, V SS Tx: Negative Analog Power Supply
Two of the six negative power supply pins are V SS Rx and V DD Rx, and they should be con-
nected to ground. These pins provide a ground reference to the analog receive and transmit
subsystems of the device, and each should be decoupled with separate 0.1 F ceramic
capacitors to V DD Rx and V DD Tx, respectively.
V DD I/O: Positive Power Supply Input/Output
Two of the five positive power supply pins are V SS I/O, and they should be connected to
+ 5 V. These pins provide power to the digital input and output circuits of the device and each
should be decoupled with a 0.1 F ceramic capacitor to V SS I/O. These pins can also be
connected to 3.3 V to provide I/O compatibility with 3 V interface devices.
V SS I/O: Negative Power Supply Input/Output
Two of the six negative power supply pins are V SS I/O, and they should be connected to
ground. These pins provide a ground reference to the digital input and output circuits of the
device, each should be decoupled with a 0.1 F ceramic capacitor to V DD I/O.
CAP3V: Core Logic Positive Power Supply
This pin is tied to the internal core logic power supply. An external 0.1 F to 1.0 F decoupling
capacitor should be connected between this pin and ground. Applications requiring a 3 V
power supply may source current from this pin. See Section 10.3, Electrical Specifications ,
for more information on the limit of the source current. This output is at 5 V until reset is
applied to the MC145572.
RESET: Reset Input
A logic 0 applied to this Schmitt trigger input pin holds the device in a hardware reset condi-
tion. A logic 1 puts the device into the normal operating state. Register NR0(b3) provides
a similar software reset function, thereby allowing control of this mode from the external
microcontroller. This pin must be held low for at least six 20.48 MHz clock periods.
During a hardware reset condition, all SCP registers are reset to their default state, and the
signals output from the DCL and FSR pins when in the MCU Master mode are halted. In
addition, the Tx driver is put into a low impedance state to terminate the U–interface and the
2B1Q receiver is unable to detect the activation wake–up tone.
NT/LT: NT/LT Select Input
A logic 1 applied to this pin puts the device into the NT mode and a logic 0 puts the device
into the LT mode. Note that Byte register 8, bit 0, also controls NT versus LT mode selection,
thereby allowing software control of this mode.
Reset must be asserted until V DD is greater than 4.75 V and the oscillator is stable.
Freescale Semiconductor, Inc.
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MC145572
CAUTION
3–5