MC145572PB Freescale Semiconductor, MC145572PB Datasheet - Page 104

• Manufacturer Part Number: MC145572PB
• Manufacturer: Freescale Semiconductor

Specifications of MC145572PB

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Not Compliant

5–32
INTERFACE
CONTROL
5.6.2
IDL2 OR GCI
INTERFACE
D out
D in
CONTROL PORT
AUTOMATIC eoc
CONTROLLER
INTERFACE &
PROCESSOR
CONTROLLER
AUTOMATIC
ACTIVATION
D CHANNEL
REGISTER
IDL2 Interface Loopback
An IDL2 interface loopback is shown in Figure 5–35. As the shaded portion of the block diagram shows,
this loopback mode takes B and D channel data in at the IDL Rx pin and sends the same data back
out the IDL2 Tx pin.
The four least significant bits of BR6 control the IDL2 Interface loopback modes. The loopback occurs
in the IDL2 interface block of the MC145572. By setting IDL2–Loop Transparent (BR6(b0)) to a 1,
the loopback is made transparent and the data input on the D in pin is transmitted onto the U–interface.
When IDL2–Loop Transparent (BR6(b0)) is reset to a 0, the data transmitted on the U–interface is
forced to idle 1s when an IDL2 interface loopback mode is enabled.
An IDL2 interface loopback is selected by setting one or more of the registers IDL2–loop B1, IDL2–loop
B2, or IDL2–loop 2B+D (BR6(b3:b1)) to a 1. To enable loopback of B1 channel data to the IDL2 inter-
face, IDL2–loop B1 (BR6(b3)) is set to a 1. To enable loopback of B2 channel data to the IDL2 inter-
face, IDL2–loop B2 (BR6(b2)) is set to a 1. To enable loopback of 2B+D data to the IDL2 interface,
IDL2–loop 2B+D (BR6(b1)) is set to a 1. The 2B+D loopback mode overrides any B1 or B2 channel
loopback that has been enabled. IDL2 interface loopback modes are independent of U–interface loop-
back modes and, as a result, these loopback modes can be operational simultaneously.
IDL2 interface loopback modes can be disabled by setting to a 1 and then resetting to a 0, the Return
to Normal bit (NR0(b0)). This clears all bits in BR6 and the crc Corrupt Control bit, (BR8(b3)). IDL2
interface loopback modes can also be cleared by resetting the appropriate bits in BR6 to a 0.
AND GCI
FIFO
FIFO
IDL2
Rx
Tx
2B + D
2B + D
Figure 5–35. IDL2 Interface Loopback Block Diagram
SUPERFRAME
Freescale Semiconductor, Inc.
FRAMER
For More Information On This Product,
SUPERFRAME
DEFRAMER
Go to: www.freescale.com
MC145572
OSCILLATOR / PLL
CRYSTAL
DAC
EQUALIZER
RECOVERY
FEEDBACK
DECISION
SLICER
TIMING
Tx FILTER
CANCELLER
FILTER
ECHO
ADC
Rx
-
XTAL in
XTAL out
DRIVER
Tx
INTERFACE
EXTERNAL
TxP
TxN
RxP
RxN
LINE
MOTOROLA
U INTERFACE