MC145572PB Freescale Semiconductor, MC145572PB Datasheet - Page 30

• Manufacturer Part Number: MC145572PB
• Manufacturer: Freescale Semiconductor

Specifications of MC145572PB

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Not Compliant

3–8
3.3.4
Control/Status Interface Pins
These pins provide a digital transfer interface for the MC145572 when configured for MCU mode.
In GCI mode, control and status information is provided over the GCI interface.
adding or subtracting a single 20.48 MHz clock period during the high time of DCL. Since
this occurs during two consecutive 8 kHz frames, the total adjustment is
basic frame. See Chapter 10, Electrical Specifications, for the locations of the timing adjust-
ment.
D out : Data Transmit Output
This pin is the output for the 2B + D data received at the U–interface. The formatting of the
data is mode dependent. In GCI mode, D out is an open drain output and must be connected
to V DD through a pullup resistor. In IDL–2 mode, D out goes high impedance when the 2B+D
transfer is complete. Refer to Chapter 5, MCU Mode Device Functionality and Chapter 8,
GCI Mode Functional Description, for more information.
D in : Data Receive Input
This pin is the input for the 2B + D data to be transmitted at the U–interface. The formatting
of the data is mode dependent. Refer to Chapter 5, MCU Mode Device Functionality and
Chapter 8, GCI Mode Functional Description, for more information. In GCI mode, D in must
be connected to V DD through a 1.5 k
SCPEN/CS/IN1
SCPCLK/R/W/IN2
SCPEN
This pin, when held low, selects the SCP for the transfer of control, status, and M channel
data information into and out of the U–interface transceiver. SCPEN should be held low
for 8 or 16 periods of the SCPCLK signal in order for information to be transferred into
or out of the MC145572. The SCP interface disregards any SCP operation that is not
exactly 8 or 16 SCPCLK clock pulses in length. If the MC145572 is the only SCP device
in the system, this pin can be tied low and bursted SCP clock can be used to access
the register.
CS
In Parallel Control Port mode, this pin acts as an active low chip select input.
IN1: Input 1
In full GCI mode, defined when MCU/GCI = 0, this is an input bit. IN1 may be read via
BR7. In NT mode, IN1 is transmitted as PS1 in the M4 maintenance bits.
SCPCLK: Serial Control Port Clock Input
This is an input to the device used for clocking data into and out of the SCP interface.
Data is clocked into the MC145572 from SCPRx on rising edges of SCPCLK. Data is
shifted out of the MC145572 SCPTx pin on falling edges of SCPCLK. SCPCLK can be
any frequency from 0 up to 4.096 MHz. An SCP transaction takes place when SCPEN
is brought low. Note that SCPCLK is ignored when SCPEN is high (i.e., it may be
continuous or it can operate in a burst mode). If the MC145572 is the only SCP device
used, the SCPEN pin can be tied low and bursted clocks applied to SCPCLK.
R/W: Parallel Control Port Read/Write
In Parallel Control Port mode, this pin functions as read versus write indication, where
write is active low.
IN2: GCI Mode Input 2
IN2 may be read via BR7. In NT mode, IN2 is transmitted as PS2 in the M4 channel
maintenance bits.
:
Parallel Control Port Chip Select
:
Serial Control Port Enable Input
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
MC145572
pull-up resistor.
97 ns, once every
MOTOROLA