MC145572PB Freescale Semiconductor, MC145572PB Datasheet - Page 68

• Manufacturer Part Number: MC145572PB
• Manufacturer: Freescale Semiconductor

Specifications of MC145572PB

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Not Compliant

Freescale Semiconductor, Inc.
TSA B1 Enable
This bit is used to enable the B1 channel in IDL2 Timeslot mode. The B1 timeslot is defined through
Overlay registers OR0 and OR3. Whenever any channel (B1, B2, or D) is enabled for Timeslot mode,
all channels enter Timeslot mode. If in Timeslot mode and TSA B1 Enable is 0, then the B1 channel
is not present on the pin D out , and the B1 channel transmit on the U–interface is actively driven to
V OH .
TSA B2 Enable
This bit is used to enable the B2 channel in IDL2 Timeslot mode. The B2 timeslot is defined through
Overlay registers OR1 and OR4. Whenever any channel (B1, B2, or D) is enabled for Timeslot mode,
all channels enter Timeslot mode. If in Timeslot mode and TSA B2 Enable is 0, then the B2 channel
is not present on the pin D out , and the B1 channel transmit on the U–interface is actively driven to
V OH .
TSA D Enable
This bit is used to enable the D channel in IDL2 Timeslot mode. The D timeslot is defined through
Overlay registers OR2 and OR5. Whenever any channel (B1, B2, or D) is enabled for Timeslot mode,
all channels enter Timeslot mode. If in Timeslot mode and TSA D Enable is a 0, then the D channel
is not present on the pin D out , and the D channel transmit on the U–interface is actively driven to
V OH .
If both TSA D Enable and D channel port Enable are set to 1, then the D channel data is presented
on both D out and DCH out , and the data transmit onto the U–interface is taken from DCH in . If the
D channel port is enabled and TSA D Enable is set to 0 (see Overlay register OR8(b0)), then the
D channel continues to operate on the D channel port and D out is high impedance during the D channel
bit time.
The clock on DCHCLK (assuming the D channel port is enabled), operates relative to FSR, based
on the timeslot programmed in the timeslot registers for the D channel.
GCI Select M4 – BR0
This bit is useful only in conjunction with full GCI mode when the pin MCU / GCI = 0. In that mode,
when this bit is set to 0, the GCI C/I channel control automatically sets and resets M4 channel control
bits pertaining to the activation state. The bits controlled by the C/I channel are: {act, dea, uoa} in
the LT mode and {act, sai} in the NT mode. Additionally, the {ps1, ps2} bits in the NT mode are
transmitted according to the state of IN1 and IN2 pin inputs. When this bit is set to 1, all M4 bits are
transmitted according to the data present in Register BR0. When operating in full GCI mode, the bit
can be set/cleared by using the monitor channel byte register read/write commands. After a hardware
or software reset this bit is 0. Normally, GCI operation does not require this bit to be set to a 1.
GCI Mode Enable
This bit makes it possible to transfer 2B + D data over the IDL2 interface as if it were in GCI mode.
This operation is established by setting the pin MCU/GCI and this bit to 1. The 2B + D data is transferred
at the timeslot indicated in OR5(2:0). The monitor and C/I channels of the GCI interface are ignored
as inputs and are not driven as outputs. Additionally, the operation of FSC, regarding its control of
the transmit superframe in Slave mode, takes precedence over the input on SFAX. See OR5 b(2:0)
for GCI slot assignment in this mode.
4.5.8
OR7: Configuration Register 1
This register is used to enable or control various modes of the MC145572. After a hardware or software
reset, all bits default to 0 to maintain MC145472/MC14LC5472 compatibility.
b7
b6
b5
b4
b3
b2
b1
b0
OR7
Internal
Line
TSEN
IDL2
IDL2 Long
M4 Trinal
crc
febe/
Analog
Connect
DCH
Rate 2
Frame
Corrupt
Mode
nebe
Loopback
Enable
Mode
Mode
Rollover
rw
rw
rw
rw
rw
rw
rw
rw
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