MC145572PB Freescale Semiconductor, MC145572PB Datasheet - Page 31

• Manufacturer Part Number: MC145572PB
• Manufacturer: Freescale Semiconductor

Specifications of MC145572PB

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Not Compliant

MOTOROLA
SCPRx/D0/OUT1
SCPTx/D1/OUT2
IRQ: Interrupt Request Output
The IRQ pin is an active low, open drain output, used to signal an external microcontroller
that an interrupt condition exists in the MC145572. On clearing the interrupt condition, the
pin is returned to the high impedance state. See the description for Nibble Register 3, Sec-
tion 4.3.4, for descriptions of the sources of interrupt conditions.
4.096 CLKOUT/D2
15.36 CLKOUT/D3
SCPRx: Serial Control Port Receive Input
SCPRx is used to input control, status, and M channel data information to the U–interface
transceiver. Data is shifted into the MC145572 on rising edges of SCPCLK. SCPRx is
ignored when data is being shifted out of SCPTx or when SCPEN is high.
D0: Data 0
In Parallel Control Port mode, this pin functions as bit 0, LSB, of the data bus.
OUT1: GCI Mode Output 1
In full GCI mode, defined by MCU/GCI = 0, OUT1 is an output reflecting the state of the
bit as set in BR7. OUT1 is also set high when the GCI Command/Indicate channel
command LTD1 is active.
SCPTx: Serial Control Port Transmit Output
SCPTx is used to output control, status, and M channel data information from the
MC145572 U–interface transceiver. Data is shifted out of SCPTx on the falling edge of
SCPCLK, most significant bit first.
D1: Data 1
In Parallel Control Port mode, this pin functions as bit 1 of the data bus.
OUT2: GCI Mode Output 2
In full GCI mode, defined by MCU/GCI = 0, OUT2 is an output reflecting the state of the
bit as set in BR7. OUT2 is also set high when the GCI Command/Indicate channel
command LTD2 is active.
4.096 CLKOUT: 4.096 MHz Buffered Clock Output
This pin provides a buffered 4.096 MHz clock output that can be used for a microcontroller
clock. This clock is not locked to the recovered clock timing. This output can be disabled
by writing a 1 to OR9(b0).
D2: Data 2
In Parallel Control Port mode, this pin functions as bit 2 of the data bus.
15.36 CLKOUT: 15.36 MHz Buffered Clock Output
This pin provides a buffered 15.36 MHz clock output that can be used for the MC145474/75
and MC145574 S/T transceiver clocks. Register BR14(b0) or Register BR15A(b2) must
be set to enable this output. This clock is a 20.48 MHz clock with every fourth clock cycle
removed. This clock is not locked to the recovered clock timing. This output can be disabled
by writing a 1 to OR9(b1). This output can be cleanly transitioned to 10.24 MHz by writing
a 1 to OR9(b3).
This pin does not provide a 50% duty cycle output. It does provide a clock that
the MC145474/75 and MC145574 can use. Figure 10–14 shows the timing of
this signal.
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MC145572
NOTE
3–9