MC145572PB Freescale Semiconductor, MC145572PB Datasheet - Page 151

• Manufacturer Part Number: MC145572PB
• Manufacturer: Freescale Semiconductor

Specifications of MC145572PB

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Not Compliant

MOTOROLA
Procedure NTINIT1()
/*
PURPOSE:
The initialization procedure NTINIT1 puts the NT configured U–interface transceiver into
automatic eoc mode and selects the M4 channel trinal consecutive check mode of operation.
It also sets default values for the M4, M5, and M6 channels. Activation interrupts are also
enabled. This routine should always be executed just prior to setting Activation Request
NR2(b3) = 1 or when the activation in progress interrupt occurs in response to the MC145572
detecting a wakeup tone.
*/
BEGIN
BR0
BR1
BR2
BR9
BR10(b0) <–
OR7(b0) <–
BR10(b0) <–
NR4
END;
Procedure NTISR1()
/*
PURPOSE:
The interrupt service routine NTISR1 handles activation and checks for Linkup with Super
frame Sync or for an Error Indication. If linkup is achieved, the febe and nebe counters
are cleared and the M4 act bit is set to a 1 if a check of the S/T–interface indicates that
it is active. If the Error Indication status bit, NR1(b2), is set to 1, appropriate mea-
sures can be taken. Also, when act = 1 from the LT, NTISR1 will enable data transparency.
*/
BEGIN
END
IF NR3(b3) = 1 THEN
BEGIN
END
IF NR3(b1) = 1 /* Test for M4 channel interrupt */
BEGIN
END
return();
<–
<–
<–
<–
<–
77;
7F;
F0;
1C;
1;
1;
0;
A;
IF NR1 = A or B AND
initial activation THEN
BEGIN
END
ELSE IF NR1 = 4 THEN
BEGIN
END
IF BR1(b7) = 1 AND
last received BR1(b7) = 0 AND /* dea = 1 from LT */
BR1(b6) = 1 THEN
ELSE
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/* M4 transmit: act = 0, power normal, normal mode (ntm = 1), warm start
/* Set initial conditions on M4 channel receive. This (BR0 = 7F) will
/* M5 and M6 channels set to ANSI T1.605–1992 reserved condition. febe
/* Select automatic eoc mode, M4 dual consecutive check, M5/M6 update on
/* Select init group registers. */
/* Enable trinal checking of M4 act, dea, and uoa bits. The remaining M4
/* Return to normal byte register operation. */
/* Enable IRQ3, activation/D channel interrupt and IRQ2 – M4 Channel
capable, unused bits = 1 */
force an M channel interrupt to occur when the M4 act bit from the LT
changes from a 0 to a 1, signifying Layer 2 communication readiness/
input = 1.*/
every frame and transmitted febe is computed nebe. */
bits are dual consecutive checked as defined in BR9(b4:b5) */
interrupt. */
BR4 <– 00;
BR5 <– 00;
IF S/T interface is
active THEN
Take appropriate measures:
* disable interrupts
* report unsuccessful
handle other M4
status changes here
activation attempt
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/* Test for activation interrupt */
BR0 <– F7;
NR2(b0) <– 1;
MC145572
/* test for act bit 0 to 1 transition and */
transparency */
/* Test for successful initial activation */
/* Clear febe counter */
/* Clear nebe counter */
/* Send M4 act status to LT */
/* Test for error indication */
/* Set Customer Enable bit for NT1 data
9–3