MC145572PB Freescale Semiconductor, MC145572PB Datasheet - Page 98

• Manufacturer Part Number: MC145572PB
• Manufacturer: Freescale Semiconductor

Specifications of MC145572PB

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Not Compliant

5–26
5.4.7
Timeslot Selection
The MC145572, operating at a DCL clock of 4.096 MHz, allows up to 256 start times for data channels
(see Table 5–6). Timeslot 0 starts immediately following the FSX/FSR pulse. Timeslot 1 is two DCL
pulses later, counted from the rising edge.
Figure 5–30 shows the relationship of the FSR and FSX pulses, DCL, and timeslot locations. Each
timeslot is on a two clock boundary, and is named TS0 to TS n – 1 , where n is the maximum number
of timeslots for the current operating data clock. A B channel occupies four contiguous 2–bit timeslots.
A D channel occupies a single 2–bit timeslot.
The following formula calculates the maximum number of timeslots for other values of DCL frequency.
B and D channel registers are programmed with the following formula.
where the x of TS x is the value programmed into a register. All numbers are programmed in hex.
Any B channel must be assigned to a timeslot at or before TS n – 4. Where TS n – 1 is the maximum
timeslot number for the current operating data clock. The three timeslots following any B channel
assignment are reserved for that B channel and may not be assigned to any other data channel.
Registers OR0 – OR5 are programmed in the above fashion.
FSR OR FSX
TIMESLOT
If timeslot assignment mode is enabled via OR6 b(7), b(6), or b(5), then the IDL2 8/10 con-
trol bit is ignored and B channel and D channel data is placed according to OR0 – OR5.
The TSEN function is available when the timeslot assigner is enabled.
B Register Value = TS x
D Register Value = TS x
DCL
Table 5–6. Maximum Number of Timeslots vs DCL Frequency
Freescale Semiconductor, Inc.
DCL Frequency
For More Information On This Product,
4.096 MHz
2.048 MHz
TS n - 1
2.56 MHz
512 kHz
16 kHz
Go to: www.freescale.com
f DCL
Figure 5–30. Timeslot Numbering
TS0
= Maximum Number of Timeslots
MC145572
Max Timeslot (Hex)
$FF
$9F
$7F
$1F
NOTE
TS1
TS2
Max Timeslot (Decimal)
255
159
127
31
TS3
TS n - 1
MOTOROLA