MC145572PB Freescale Semiconductor, MC145572PB Datasheet - Page 152

• Manufacturer Part Number: MC145572PB
• Manufacturer: Freescale Semiconductor

Specifications of MC145572PB

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Not Compliant

9–4
9.2.2
NT Non-Automatic eoc Mode Initialization and Activation
The MC145572 can be operated with eoc frame trinal checking and eoc interrupts enabled so an
external microcontroller may handle all eoc commands in software. Note that the MC145572 still per-
forms eoc frame trinal checking, thus relieving the external microcontroller of this task. The M4 channel
dual consecutive check mode is enabled. The examples in this section configure an NT U–interface
transceiver in these modes and activate it.
The eoc message processor, given as an example here, covers a very limited implementation of an
eoc command set.
The activation procedure, NTACT2, resets the U–interface transceiver, calls the initialization routine
NTINIT2, sets activate request, and waits for interrupts.
An initialization and activation procedure for an NT1 follows with numbers in hexadecimal. A suggested
interrupt service routine outline, NTISR2, is also given.
Procedure NTACT2();
/*
PURPOSE:
The activation procedure NTACT2 resets the U–interface transceiver, calls the initializa-
tion routine NTINIT2, sets activate request, and waits for interrupts.
*/
BEGIN
NR0(b3) <–
NR0(b3) <–
CALL NTINIT2();
If NR1 = 0 then NR2 (b3) <– 1;
Wait for interrupt;
Other code;
END;
Procedure NTINIT2()
/*
PURPOSE:
The initialization procedure NTINIT2 puts the NT configured U–interface transceiver into
eoc trinal–check mode and selects the M4 channel trinal consecutive check mode of opera-
tion. It also sets default values for the M4, M5, and M6 channels. Activation interrupts
are also enabled. This routine should always be executed just prior to setting Activation
Request NR2(b3) = 1 or when the activation in progress interrupt occurs in response to the
MC145572 detecting a wakeup tone.
*/
BEGIN
BR0
BR1
BR2
BR9
BR10(b0) <–
OR7(b0) <–
BR10(b0) <–
NR4
END;
<–
<–
<–
<–
<–
1;
0;
77;
7F;
F0;
9C;
1;
1;
0;
E;
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/* Assert software reset. Only required
/* De–assert software reset. Only required at power–up initialization/
/* M4 transmit: act = 0, power normal, normal mode (ntm = 1), warm start
/* Set initial conditions on M4 channel receive. This (BR0 = 7F) will
/* M5 and M6 channels set to ANSI T1.605–1992 reserved condition. febe
/* Select non–automatic eoc mode, M4 dual consecutive check, M5/M6 up-
/* select init group registers */
/* enable trinal checking of M4 act, dea, and uoa bits. The remaining M4
/* return to normal byte register operation */
/* Enable activation/D channel, M4 channel and eoc interrupts */
at power–up initialization/
/*
capable, unused bits = 1 */
force an M channel interrupt to occur when the M4 act bit from the LT
changes from a 0 to a 1, signifying Layer 2 communication readiness/
input = 1.*/
date on every frame and transmitted febe is computed nebe. */
bits are dual consecutive checked as defined in BR9(b4:b5) */
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MC145572
/*
Set activation request bit */
Wait for result of Activation */
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