MC145572PB Freescale Semiconductor, MC145572PB Datasheet - Page 57

• Manufacturer Part Number: MC145572PB
• Manufacturer: Freescale Semiconductor

Specifications of MC145572PB

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Not Compliant

MOTOROLA
4.4.10
transmits the crc and this bit is set, the transmitted crc is inverted. This bit can be cleared or set
at any time during transmission of a superframe. This bit functions the same as in the MC145472/
MC14LC5472 after a Hardware Reset (RESET). When OR7(b2) is set to 1, the operation of this bit
is modified so that the outgoing crc is only corrupted on the current superframe.
Match Scrambler
When set to 1, this bit forces the descrambler and scrambler polynomials to match. This is used for
external analog loopback and framer–to–deframer loopback.
Receive Window Disable
When set to 1, this bit disables the search window placed around the received synchronization word
in the LT mode. When the receive window is disabled, the LT will synchronize to an incoming syn-
chronization word that is located at any arbitrary point with respect to its transmitted synchronization
word. This allows the U–interface transceiver to use its own transmitted synchronization word for frame
detection when operated in external analog loopback mode and framer–to–deframer loopback.
NT/LT Invert
This bit allows override control of the setting of the NT or LT operation of the U–interface transceiver’s
external NT/LT mode pin. If this bit is 0 and the NT/LT pin is high, the device is in NT mode. When
this bit is then set to 1, the device will then be in the LT mode.
NT/LT Mode
This read–only bit reflects the current mode of the device. If 1, the U–interface transceiver is operating
in the NT mode.
BR9: Maintenance Channel Configuration Register
This register contains mode control over the deframer’s updating of the received maintenance bits.
The register is cleared on Software Reset (NR0(b3)) or Hardware Reset (RESET). When BR10(b0)
= 1 this register is replaced by Register OR9.
eoc Control 1:0
These bits control the eoc handling capability of the U–interface transceiver. Table 4–9 gives a brief
description of each mode selected by the eoc Control bits. The eoc Trinal–Check mode (b7,b6 = 1,0)
and the Automatic eoc Processor mode (b7,b6 = 0, “Don’t Care”) are described in the paragraphs
following Table 4–9. The default mode setting is 0,0; thereby selecting the Automatic eoc Processor.
Regardless of the operating mode, every time R6 is loaded by the deframer, IRQ2 (NR3(b2)) is set
to 1. Use the update on every frame mode (b7,b6 = 1,1) for digital loop carrier or proprietary ap-
plications.
BR9
b7
eoc Control 1:0
1
1
0
Control 1
Don’t Care
eoc
b7
b6
See Appendix C for printed circuit board layout recommendations.
1
0
Freescale Semiconductor, Inc.
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For More Information On This Product,
Control 0
Update eoc register (R6) on every eoc frame (twice during each superframe). Recommended
for Digital Loop Carrier applications.
Update eoc register (R6) after passing a trinal–check.
Update eoc register (R6) after passing a trinal–check and also invoke Automatic eoc
Processor to operate when in NT mode.
eoc
b6
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Table 4–9. eoc Control Modes
Control 1
M4
b5
MC145572
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CAUTION
Control 0
M4
b4
eoc Function Description
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Control 1
M5/M6
b3
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Control 0
M5/M6
b2
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Control
febe/
nebe
b1
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Reserved
b0
4–21