MC145572PB Freescale Semiconductor, MC145572PB Datasheet - Page 12

• Manufacturer Part Number: MC145572PB
• Manufacturer: Freescale Semiconductor

Specifications of MC145572PB

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Not Compliant

Figure
Figure 5–37.
Figure 6–1.
Figure 7–1.
Figure 7–2.
Figure 7–3.
Figure 8–1.
Figure 8–2.
Figure 8–3.
Figure 8–4.
Figure 8–5.
Figure 8–6.
Figure 8–7.
Figure 8–8.
Figure 8–9.
Figure 8–10.
Figure 8–11.
Figure 8–12.
Figure 8–13.
Figure 8–14.
Figure 8–15.
Figure 8–16.
Figure 8–17.
Figure 8–18.
Figure 8–19.
Figure 9–1.
Figure 9–2.
Figure 9–3.
Figure 10–1.
Figure 10–2.
Figure 10–3.
Figure 10–4.
Figure 10–5.
Figure 10–6.
Figure 10–7.
Figure 10–8.
Figure 10–9.
Figure 10–10. SFAX Input Timing in IDL2 (Master or Slave) Short Frame Mode
Figure 10–11.
Figure 10–12. SFAX/SFAR Output Timing in IDL2 Short Frame Mode (Master or Slave)
Figure 10–13. SFAX/SFAR Output Timing in IDL2 Long Frame Mode (Master or Slave)
Figure 10–14. Parallel Control Port Write Timing
Figure 10–15. Parallel Control Port Read Timing
Contents–viii
Title
External Analog Loopback Block Diagram
ANSI U–Interface Transceiver Activation State Diagram
Maintenance Channel Interrupt Timing
NT Mode Maintenance Channel Updates
LT Mode Maintenance Channel Updates
MC145572 Configuration for GCI Operation
Single Channel GCI Format
Multiplexed GCI Format Example
Monitor Channel Access Protocol
Monitor Channel Protocol with Delay
Monitor Channel Register Write Sequence
Monitor Channel Register Read Sequence
Monitor Channel Multiple Interrupt Indications Sequence
Time Diagram for Total Activation Initiated by the Network
Time Diagram for Total Activation Initiated by the Terminal Equipment
Time Diagram for Deactivation (Always Initiated by the Network)
Time Diagram of a U–Only Activation (Always Initiated by the Network)
Time Diagram for a Transition from DSL–Only Activation to Total Activation Initiated by
the Network
Time Diagram for a Transition from DSL–Only Activation to Total Activation Initiated by
the Terminal Equipment
Time Diagram for a Transition from Total Activation to DSL–Only Activation
(Always Initiated by the Network)
Time Diagram for Activation with Loopback 2 (Always Initiated by the Network)
Time Diagram for Execution of Loopback 2 Once Link is Active
(Always Initiated by the Network)
NT Mode GCI State Diagram
LT Mode GCI State Diagram
Status Information Flow in a 4:1 Pair–Gain Application
IDL Short Frame Sync Master Timing, 8– and 10–Bit Formats and TSAC Formats
IDL Short Frame Sync Slave Timing, 8– and 10–Bit Formats
Long Frame Sync Master Timing, 8– and 10–Bit Formats
Long Frame Sync Slave Timing, 8– and 10–Bit Formats
GCI Timing
IDL2 (Master or Slave) Short Frame Sync 8–Bit Format, D Channel Port Timing
IDL2 (Master or Slave) Short Frame Sync 10–Bit Format, D Channel Port Timing
IDL2 (Master or Slave) Long Frame Sync 8–Bit Format, D Channel Port Timing
IDL2 (Master or Slave) Long Frame Sync 10–Bit Format, D Channel Port Timing
SFAX Input Timing in IDL2 (Master or Slave) Long Frame Mode
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LIST OF FIGURES (Continued)
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Freescale Semiconductor, Inc.
For More Information On This Product,
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Go to: www.freescale.com
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MC145572
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