MC145572PB Freescale Semiconductor, MC145572PB Datasheet - Page 114

• Manufacturer Part Number: MC145572PB
• Manufacturer: Freescale Semiconductor

Specifications of MC145572PB

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Not Compliant

6–4
6.6
6.7
After the MC145572 ends transmission of SN1 it waits up to 480 ms for LT to transmit a signal, SL1 or
SL2. The MC145572 then recovers timing information and transmits SN2. When full duplex operation
has been achieved, bits NR1(b3, b1, b0) are each set to a 1 and SN3 is enabled for transmission. SN3
is transmitted with only the maintenance channel bits active until transparent 2B+D transmission is
enabled by setting Customer Enable (NR2(b0)) to a 1, or the M4 channel act bit has been received
when the MC145572 is configured for the Verified act mode. See BR9(b5,b4) for more about Verified
act.
If SN3 is not reached within 15 seconds, activation is automatically aborted, Error Indication (NR1(b2))
is set to a 1, and bits NR1(b3, b1, b0) are each reset to a 0. The 15–second activation timer is started
when Activation in Progress (NR1(b0)) is set to a 1. The Activation Request bit (NR2(b3)) is internally
reset to a 0 when Activation in Progress (NR1(b0)) is set to a 1.
ACTIVATION OF U-INTERFACE BY LT
LT mode activation initiation is accomplished by setting Activation Request (NR2(b3)) to a 1. The LT
initiates activation of the U–interface by transmitting TL for a period of two frames (3 ms) toward NT.
At this time, the LT U–interface transceiver also sets Activation in Progress (NR1(b0)) to a 1. After
LT stops sending TL, the NT transmits TN and SN1 and trains its echo cancellers. The LT then waits
for loss of the far–end signals, TN and SN1.
Loss of TN and SN1 reception is immediately followed by the LT transmission of SL1, while the LT
end echo cancellers are trained. From Figure 6–1, it can be seen that the LT transceiver has a period
of time during activation where the NT end is guaranteed to be quiet. This is to permit the MC145572
to train its echo cancellers during the transmission of SL1 and part of SL2. During SL2, the MC145572
looks for a far–end signal. The MC145572 then recovers timing information and trains for full duplex
operation. When full duplex operation has been achieved, NR1(b3, b1, b0) are each set to a 1 and
SL3 is transmitted with the M channel bits active. The 2B+D channels become active when Customer
Enable (NR2(b0)) is set to a 1.
If activation continues for more than 15 seconds it is aborted, Error Indication (NR1(b2)) is set to a
1, and bits NR1(b3,b1,b0) are each reset to a 0. The 15–second activation timer is started when Activa-
tion in Progress (NR1(b0)) is set to a 1. Activation Request (NR2(b3)) is internally reset to a 0 when
Activation in Progress (NR1(b0)) is set to a 1.
ACTIVATION INDICATION
The Linkup status bit (NR1(b3)) is used to signify that the loop is active. With MC145572 configured
as an NT, this corresponds to NT transmitting SN3 and receiving SL3. With MC145572 configured
as an LT, this corresponds to LT transmitting SL3 and receiving SN3. When the U–interface is fully
active, Superframe Sync (NR1(b1)) and Linkup (NR1(b3)) are set to a 1.
When the LT U–interface transceiver is activated and ready to pass 2B+D data, the M4 channel act
bit should be set per ANSI T1.601–1992. This is done by setting BR0(b7) to a 1. Also, it is required
that Customer Enable (NR1(b0)) be set to a 1 when the M4 channel verified act/dea mode is not
enabled. This must be done after activation from the receive RESET state. Refer to Section 4.4.10,
for more details on Verified act/dea and control of M4 channel bits.
Whenever the MC145572 detects loss of Superframe Synchronization, NR1 becomes $8 and an in-
terrupt is generated if enabled. This indicates that loss of Superframe Synchronization has been
detected. When Superframe Synchronization is lost for more than 480 ms, MC145572 always deac-
tivates and sets NR1 = $4 error indication, and issues an interrupt if enabled. When the error condition
causing loss of Superframe Synchronization goes away before 480 ms has elapsed, NR1 returns to
$B and an interrupt is generated if enabled. It is not necessary to set Customer Enable (NR2(b0)) to
a 1 when NR1 returns to $B.
The MC145572 continually monitors the error on its recovered signal. If the internally monitored error
rate becomes too large, MC145572 loses data transparency and NR1 changes to $A or $8 and issues
an interrupt. Note that loss of Superframe Synchronization always means that data transparency is
lost, but loss of data transparency does not always mean that Superframe Synchronization is lost.
Also, note that loss of signal always means that Superframe Synchronization is lost. There is no time
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MC145572
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