MC145572PB Freescale Semiconductor, MC145572PB Datasheet - Page 77

• Manufacturer Part Number: MC145572PB
• Manufacturer: Freescale Semiconductor

Specifications of MC145572PB

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Not Compliant

MOTOROLA
5.3.1
SCP Mode
The MC145572 is equipped with an industry standard SCP interface. The SCP is used by an external
controller, such as an M68HC05 family microcontroller, MC145488 Dual Data Link Controller, or
MC68302 Integrated Multiprotocol Processor, to communicate with the U–interface transceiver.
The SCP is a full–duplex four–wire interface with control and status information passed to and from
the U–interface transceiver. The SCP interface consists of a transmit output, a receive input, a data
clock, and an enable signal. These device pins are known as SCPTx, SCPRx, SCPCLK, and SCPEN,
respectively. The SCP Clock determines the rate of exchange of data in both the transmit and receive
directions, and the SCP Enable signal governs when this exchange is to take place. The four–wire
SCP interface is supplemented with an interrupt request line, IRQ, for external microcontroller notifi-
cation of an event requiring service.
The operation and configuration of the U–interface transceiver is controlled by setting the state of
the control registers within the U–interface transceiver and monitoring the status registers. The control,
status, and M channel data registers reside in six 4–bit wide nibble registers, one 12–bit wide nibble
register, and twenty–nine 8–bit wide byte registers. A complete register map and detailed register
descriptions can be found in Chapter 4. Figure 5–2 shows pin configurations to operate MC145572
in IDL2 mode using the SCP for access to the register set. See Chapter 10 for the SCP timing
diagrams.
NOTE: In LT mode, the 100 k resistor on SFAX/TxSFS is required when none of these pin functions is enabled.
8 kHz REFERENCE
20.48 MHz
100 k
0.1 F
Freescale Semiconductor, Inc.
For More Information On This Product,
Figure 5–2. MCU Mode with SCP Configuration
+ 5 V
17
21
20
18
19
34
35
38
39
40
41
25
26
33
32
42
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8
7
IRQ
SCPEN
SCPCLK
SCPRx
SCPTx
4.096 CLKOUT
15.36 CLKOUT
BUFXTAL
DCHCLK
DCH in
DCH out
SFAR
SFAX/TxSFS
V ref P
V ref N
XTAL in
XTAL out
FREQREF
MC145572
MC145572FN
MCU/GCI
PAR/SER
V DD I/O
V DD I/O
V DD Rx
V SS I/O
V SS I/O
RESET
CAP3V
V DD Tx
V SS Rx
V SS Tx
NT/LT
V DD
D out
V SS
V SS
FSR
FSX
DCL
RxP
RxN
M/S
TxP
TxN
D in
1
22
44
2
11
10
3
4
24
23
37
36
14
15
43
13
16
27
28
31
30
29
9
12
5
6
8 kHz
8 kHz
256 kHz . . . 4096 kHz
COUPLING
0 V/+ 5 V
+ 5 V
CIRCUIT
0.1 F
+ 5 V
T
R
5–5