MC145572PB Freescale Semiconductor, MC145572PB Datasheet - Page 50

• Manufacturer Part Number: MC145572PB
• Manufacturer: Freescale Semiconductor

Specifications of MC145572PB

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Not Compliant

4–14
4.4.5
4.4.6
a 0 for two consecutive superframes. This bit is updated at the end of the first frame of each super-
frame and is provided in this register for status only. See BR9(b5:b4) for more information regarding
this bit. When OR7(b0) is set, the M4 act and dea bits must be valid for three superframes before
Verified act or Verified dea are updated.
Verified dea
This is the dual–consecutively checked, inverted setting of the dea bit, in the received superframe.
Since the dea bit can only be received by an NT, this bit can only be 1 in the LT mode. Dual–consecutive
checking requires that the received bit is in the same state for two consecutive superframes. Whenever
the U–interface transceiver detects a transition from 0 to 1 on Superframe Sync in NR1(b1), Verified
dea is set to 0. It remains in its current state until both Superframe Sync (NR1(b1)) and Linkup
(NR1(b3)) are 1s. Then, if the received dea bit is 0 for two consecutive superframes, Verified dea
will become 1. After Verified dea becomes 1, if the received dea bit is ever 1 for two consecutive
superframes, then Verified dea will become a 0. This bit is updated at the end of the second basic
frame of each superframe and is provided in this register for status only. See BR9(b5:b4) for more
information regarding this bit. When OR7(b0) is set, the M4 dea bit must be valid for three superframes
before Verified dea is updated.
Superframe Detect
This is the unmodified output of the Superframe Deframer’s superframe detection circuit. It is primarily
intended for diagnostic purposes.
BR4:
This register contains the current febe count. The counter is not cleared by a software or hardware
reset. The register can be preset to any value by writing to it. If the febe bit is active in a superframe,
the counter will increment at the end of the received superframe. The counter will not increment unless
Superframe Sync (NR1(b1)) and Linkup (NR1(b3)) are both 1s. If OR7(b1) is set, then the febe counter
will roll over from $FF to $00. The user software must take into account that if OR7(b1) is set, the
counter value read from BR4 might be less than the previous value, which means that the counter
has rolled over. The default setting for OR7(b1), after any hardware or software reset, produces the
same operation as the MC145472/MC14LC5472. This register is replaced by Register OR4 when
BR10(b0) = 1. When OR7(b1) is cleared, BR4 counts to $FF and does not roll over. This is the default
configuration after any reset to maintain MC145472 compatibility.
BR5:
This register contains the current nebe count. A nebe occurs whenever the received crc message
does not match the computed crc or when Linkup (NR1(b3)) is 1 and Superframe Sync (NR1(b1))
is 0. The Superframe Framer maintains the superframe timing to increment the nebe counter when
Superframe Sync is 0. The counter is not cleared by a software or hardware reset. The register can
be preset to any value by writing to it.
When the Superframe Deframer detects a crc error in the received superframe, the counter is increm-
ented at the end of that superframe. When OR7(b1) is set, then the febe counter rolls over from
$FF to $00. The user software must take into account that if OR7(b1) is set, the counter value read
from BR5 might be less than the previous value, which means that the counter has rolled over. The
default setting for OR7(b1), after any hardware or software reset, produces the same operation as
the MC145472/MC14LC5472. When BR10(b0) = 1, this register is replaced by Register OR5. When
BR4
febe
nebe
Counter 7
febe
b7
Counter
Counter
Freescale Semiconductor, Inc.
rw
For More Information On This Product,
Counter 6
febe
b6
Go to: www.freescale.com
rw
Counter 5
febe
MC145572
b5
rw
Counter 4
febe
b4
rw
Counter 3
febe
b3
rw
Counter 2
febe
b2
rw
Counter 1
febe
b1
rw
MOTOROLA
Counter 0
febe
b0
rw