MC145572PB Freescale Semiconductor, MC145572PB Datasheet - Page 106

• Manufacturer Part Number: MC145572PB
• Manufacturer: Freescale Semiconductor

Specifications of MC145572PB

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Not Compliant

5–34
5.6.4
The procedure to enable the Superframe Framer–to–Deframer loopback for a single LT–configured
U–interface transceiver follows, with all numbers given in hexadecimal.
To turn off the Superframe Framer–to–Deframer loopback.
Superframe Framer-to-Deframer Loopbacks in Systems Having
Multiple MC145572s
This section describes how to enable the Superframer Framer–to–Deframer loopback in applications
where multiple MC145572s are normally operated in NT mode. A typical application is remote access
equipment having four to eight MC145572 devices connected to a single time division multiplex bus.
This time division mutliplex bus is connected to either an MPC860MH or 68MH360. The purpose of
this section is to ensure that the DCL and FSR signal timing to the MC145572 device on which the
loopback is being performed is derived from that same MC145572.
In NT systems, the 20.48 MHz clocks of the individual MC145572s are not synchronized to each other
when all the transceivers are deactivated. Thus, when performing a Superframer Framer–to–Deframer
loopback (or external analog loopback), a specific transceiver’s DCL and FSR/FSX signals must not
be traceable to another MC145572. This ensures that clock slips do not occur between the DCL/FSR
signals and the 20.48 MHz clock of the MC145572 device under test.
In LT mode configurations, this is normally not a problem, since all of the MC145572s have their
20.48 MHz oscillators locked to system backplane timing. There will never be any clock slips.
Systems having multiple NT mode U transceivers on a TDM bus come in two types of architectures.
In either type of system architecture, the Superframe Framer–to–Deframer loopback can be done
on only one MC145572 at a time.
NR0 = 8
NR0 = 0
BR14 = 10
BR8 = B6
BR12 = 89
BR13 = 0C
NR2 = 1
BR14 = $00
BR8 = $00
BR12 = $00
BR13 = $00
System Type No. 1: One U transceiver is configured as the TDM master and the others are
configured as TDM slaves.
System Type No. 2: All U transceivers are configured as TDM slaves (M/S pin connected to
V SS ). One U transceiver is selected to provide a locked system clock from which is derived the
DCL and FSR/FSX signals that are provided to all U transceivers. Typically in such systems,
there is a mux that allows the locked clock to be selected from one of the U transceivers. This
allows any transceiver to provide the master clock. The clock source can come from the
FREQREF pin (see OR8(b4) description), BUFXTAL pin, or SYSCLK pin.
System Type No. 1: The transceiver on which the loopback test is performed is put into TDM
master mode. This is done by connecting the M/S pin to V DD or setting BR7(b1) to a 1, in the
case of the M/S pin hardwired to V SS . The other MC145572s are put into slave mode.
System Type No. 2: Enable the mux to select its reference clock source from the transceiver on
which the loopback test is being performed.
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Assert reset, not required.
Deassert reset, not required.
Enable Framer–to–Deframer Loopback, Enable CLKs. Enable CLKs is
optional and enables SYSCLK to display an Eye Pattern.
Match Polynomials, Receive Window Disable, do not set NT/LT
Invert, transmit Frame Control state SL3.
Control Steer, Hold Activation State, Force Linkup.
Accumulate DFE Output and Enable DFE Updates. Disable Echo
Cancellers.
Set Customer Enable.
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MC145572
MOTOROLA