MC145572PB Freescale Semiconductor, MC145572PB Datasheet - Page 11

• Manufacturer Part Number: MC145572PB
• Manufacturer: Freescale Semiconductor

Specifications of MC145572PB

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Not Compliant

Figure
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MOTOROLA
Title
ISDN Reference Model
MC145572 Typical ISDN Applications
Pair Gain Application, Central Office Terminal
Pair Gain Application, Remote Terminal
Method to Drive MC145572 with External Clock
IDL2 Interface Loopback Control Bits
IDL2 Interface Loopback Logic Diagram
IDL2 Interface Timing in 8–Bit Master Mode
IDL2 Interface Timing in 10–Bit Master Mode
MC145572 Functional Block Diagram
MCU Mode with SCP Configuration
SCP Nibble Registers 0 – 5, Write Operation
SCP Nibble Registers 0 – 5, Read Operation
SCP eoc Register R6 Write Operation Using Double 8–Bit Transfer
SCP eoc Register R6 Read Operation Using Double 8–Bit Transfer
SCP eoc Register R6 Write Operation Using Single 16–Bit Transfer
SCP eoc Register R6 Read Operation Using Single 16–Bit Transfer
SCP Byte Register Write Operation Using Double 8–Bit Transfer
SCP Byte Register Read Operation Using Double 8–Bit Transfer
SCP Byte Register Write Operation Using Single 16–Bit Transfer
SCP Byte Register Read Operation Using Single 16–Bit Transfer
MCU Mode with PCP Configuration
PCP Mode Nibble Register Write and Read Operations
PCP Register R6 Write and Read Operations
PCP Byte Register Write Operation
IDL2 Interface Timing in Short Frame Master Mode, 8–Bit Frames
IDL2 Interface Timing in Short Frame Master Mode, 10–Bit Frames
IDL2 Interface Timing in Short Frame Slave Mode, 8–Bit Frames
IDL2 Interface Timing in Short Frame Slave Mode, 10–Bit Frames
IDL2 Interface Timing in Long Frame, 8–Bit Frames
IDL2 Interface Timing in Long Frame, 10–Bit Frames
IDL2 GCI 2B+D Data Formats
D Channel Port Timing, IDL2 10–Bit Frames
D Channel Port Timing, IDL2 8–Bit Frames
D Channel Port Timing, IDL2 GCI 2B+D Frames
Timeslot Assigner Data Format Example
Timeslot Assigner Data Format Example, B2 Channel Not Enabled
Timeslot Assigner Example with D Channel Port Enabled
Timeslot Numbering
SFAR Timing
SFAX Timing
IDL2 GCI 2B+D Format Superframe Alignment Signal
U–Interface Loopback Block Diagram
IDL2 Interface Loopback Block Diagram
Superframe Framer–to–Deframer Loopback Block Diagram
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Freescale Semiconductor, Inc.
For More Information On This Product,
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LIST OF FIGURES
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Go to: www.freescale.com
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MC145572
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