MC145572PB Freescale Semiconductor, MC145572PB Datasheet - Page 49

• Manufacturer Part Number: MC145572PB
• Manufacturer: Freescale Semiconductor

Specifications of MC145572PB

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Not Compliant

MOTOROLA
4.4.3
4.4.4
BR2: M5/M6 Transmit Data Register
This register contains the reserved M5 and M6 bits that are sent by the Superframe Framer. The bits
written to the register are sent out on the next transmit superframe boundary, if Superframe Update
Disable (NR2(b1)) is set to 0. All bits are set to 1s following a Hardware Reset (RESET) or Software
Reset (NR0(b3)). See BR9(b1) for details concerning use of the far–end block error (febe) Input,
b4. Bits b7, b6, and b5 are double buffered. When BR10(b0) = 1, this register is replaced by Register
OR2.
febe Input
The value in this bit is enabled to be transmitted as febe when BR9(b1) is set to 1.
BR3: M5/M6 Receive Data Register
This register contains the ANSI T1.601–1992 reserved M5 and M6 bits that are received by the
Superframe Deframer, occurring in basic frames 1 and 2 of the superframe, and four other Superframe
Deframer status bits. The M5 and M6 values in the register are valid when the Superframe Sync
bit, NR1(b1), is 1. M50, M51, and M60 are updated, based on the mode set in Register BR9(b3:b2).
Bits b7, b6, and b5 are double buffered. They can be read at any time during the superframe prior
to the next update. It is recommended that this register be read as soon as possible after an M5/M6
channel interrupt. Refer to the description of BR9(b3:b2) for details concerning the operation of these
three bits. When BR10(b0) = 1, this register is replaced by Register OR3.
Received febe
This is the state of the received febe bit in the last complete received superframe. It is updated at
the end of each received superframe when Superframe Sync (NR1(b1)) and Linkup (NR1(b3)) are
both 1s.
Computed nebe
This is the state of the cyclic redundancy check (crc) check from the last complete received super-
frame. It is updated at the end of each received superframe. This bit is 0 when a crc error is detected.
Also, when either Superframe Sync (NR1(b1)) or Linkup (NR1(b3)) is 0, this computed near–end block
error (nebe) bit is forced to 0.
Verified act
This is the dual–consecutively checked setting of the act bit in the received superframe. Dual–con-
secutive checking requires that the received bit be in the same state for two consecutive superframes.
Whenever the U–interface transceiver detects a transition from 0 to 1 on Superframe Sync, NR1(b1),
Verified act is set to 0. It remains in its current state until both Superframe Sync (NR1(b1)) and Linkup
(NR1(b3)) are 1s. Then, if the received act bit is 1 for two consecutive superframes, Verified act
becomes a 1. After Verified act becomes a 1, it changes to 0 if the received act bit is received as
ANSI T1.601–1992 presently reserves bits M50, M60, and M51. Therefore, these bits should be set to 1s for ISDN
applications.
BR2
BR3
Reserved bits b0, b1, b2, and b3 should be set to 0 at all times to maintain future com-
patibility.
M50
M50
b7
b7
ro/wo
Freescale Semiconductor, Inc.
rw
For More Information On This Product,
M60
b6
M60
b6
ro/wo
rw
Go to: www.freescale.com
M51
b5
M51
b5
MC145572
ro/wo
rw
febe Input
CAUTION
Received
febe
b4
b4
ro
rw
Computed
Reserved
febe
b3
b3
rw
ro
Reserved
Verified
act
b2
b2
rw
ro
Reserved
Verified
dea
b1
b1
ro
rw
Reserved
Super-
Detect
frame
b0
b0
rw
ro
4–13