MC145572PB Freescale Semiconductor, MC145572PB Datasheet - Page 61

• Manufacturer Part Number: MC145572PB
• Manufacturer: Freescale Semiconductor

Specifications of MC145572PB

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Not Compliant

MOTOROLA
4.4.12
Select Dump Access
This bit hides the normal byte register BR13, and the register becomes a byte–wide access port, OR13,
to the dump/restore mechanism of the U–chip. Two more bits in the overlay registers control the operat-
ing mode of the dump/restore mechanism. See Overlay register OR8. This bit is reset by hardware
reset only.
Select DCH Access
This bit hides the normal byte register, BR12, and the register becomes an 8–bit read–only/write–only
register, OR12, and provides access to the D channel. When this bit is asserted, D channel input
data present on the pin interfaces of the MC145572 is ignored and D out is high impedance. Instead,
the D channel is sourced strictly from this register. D channel data received from the U–interface main-
tains correct byte alignment relative to the U–interface basic frame boundary on the pin interfaces,
and is readable through the overlay register, OR12, eight bits at a time. IRQ3 is used to indicate when
every new eight bits of data are received, in addition to indicating a change in receive status.
A special code (1111) is loaded in Nibble register NR1, to indicate that the source of the interrupt
is the D channel access register. Both transmit and receive of the D channel data is aligned respective
to the transmit and receive superframes. When selected, the D channel access register has the highest
priority over other possible routes (e.g., the IDL2 interface and the D channel port), for the D channel
data. This bit is reset by hardware reset only. Software should read and write this register at the time
the D channel interrupt occurs.
Enabling OR12 access, enables the D channel interrupt onto IRQ3. The interrupt must still be enabled
via IRQ3 Enable in NR4 for the IRQ pin to become active. Upon receipt of the interrupt, the external
controller must read the interrupt status in NR3 to determine that it is an IRQ3. The controller must
then read NR1, where it would find the code 1111, indicating the actual source is a D channel interrupt.
Select Overlay
This bit hides the normal byte registers BR0 – BR9, and the registers become the overlay registers
OR0 – OR9. In general, the overlay registers contain device information that needs to be set only
once following reset, such as the timeslot information or during some test mode. This bit is reset by
hardware reset only.
BR11: Activation State Register
This register contains activation state and control data. All the bits are cleared on Hardware Reset
(RESET) and Software Reset (NR0(b3)). The register is a read–only/write–only register. Setting
BR14(b6) to 1 permits the external microcontroller to read back the write portion of the register.
Activation Control 6:0
These write–only bits allow the external microcontroller to set a new activation state for the U–interface
transceiver to execute. The transition to this state is controlled by BR12. Use of this register is not
required for normal operation.
BR11
If DCH Access mode is used in conjunction with timeslot assignment, the D channel time-
slot must not be timeslot 0 in order to maintain synchronization with the transmit super-
frame. This is especially true in LT mode when SFAX is used as an input.
Activation
Activation
Control 6
State 6
b7
Freescale Semiconductor, Inc.
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For More Information On This Product,
Activation
Activation
Control 5
State 5
b6
Go to: www.freescale.com
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Activation
Activation
Control 4
State 4
b5
MC145572
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Activation
Activation
Control 3
State 3
NOTE
b4
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ro
Activation
Activation
Control 2
State 2
b3
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ro
Activation
Activation
Control 1
State 1
b2
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ro
Activation
Activation
Control 0
State 0
b1
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Activation
Activation
Disable
Expire
Timer
Timer
b0
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4–25