MC145572PB Freescale Semiconductor, MC145572PB Datasheet - Page 156

• Manufacturer Part Number: MC145572PB
• Manufacturer: Freescale Semiconductor

Specifications of MC145572PB

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Not Compliant

9–8
9.3
TIMESLOT ASSIGNER PROGRAMMING EXAMPLE
In modern Central Office Switches (COS) or Private Branch Exchanges (PBXs), a Time Division Multi-
plex (TDM) bus may carry data from several different U–interfaces. The MC145572 is designed with
a flexible Timeslot Assigner (TSAC), allowing it to transmit and receive 2B+D data in any timeslot
on a TDM bus.
With the MC145572s TSAC, B, and D channel timeslots can be assigned an any 2–bit boundary.
Figure 9–1 shows an 8 kHz TDM frame divided into 2–bit timeslots labeled TS0 through TSn–1. ‘n’
is the maximum number of 2–bit timeslots. Programming the MC145572s TSAC is accomplished by
writing the 2–bit timeslot number that corresponds to the first two bits of a B or D channel timeslot
to one of the TSAC registers (OR0 through OR5).
A typical arrangement of timeslots for four U–interface devices is shown in Figure 9–2. The procedure
TSACinit() shows how to configure the MC145572 as if it occupies the timeslots highlighted in
Figure 9–2.
Procedure TSACinit();
/*
PURPOSE:
INITIAL CONDITIONS:
TIMESLOT assignment
B1 channel transmit –> TS8 through TS11
B1 channel receive
B2 channel transmit –> TS12 through TS15
B2 channel receive
D channel transmit
D channel receive
The transmit and receive starting timeslot for each channel is programmed into registers
OR0 through OR5.
*/
Begin
NR0(b3) <–
NR0(b3) <–
BR10(b0) <–
OR0
OR1
OR2
OR3
OR4
OR4
OR6
OR10(b0) <–
End;
select IDL format and timeslots for B1, B2, and D channels
MC145572 configured for IDL–2 slave mode
DCL clock rate = 4.096 MHz
<–
<–
<–
<–
<–
<–
<–
1;
0;
1;
08;
0C;
11;
08;
0C;
11;
E0;
0;
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/* Assert software reset. Only required
/* De–assert software reset. Only required at power–up initialization.*/
/* Select Init Group Overlay registers.*/
/* B1 transmit starts in TS8 */
/* B2 transmit starts in TS12 */
/* D transmit is in TS33 */
/* B1 receive starts in TS8 */
/* B2 receive starts in TS12 */
/* D receive is in TS33 */
/* Enable B1, B2, and D timeslots.*/
/* Timeslot initialization over. Deselect overlay registers and return
–> TS8 through TS11
–> TS12 through TS15
–> TS33
–> TS33
at power–up initialization.*/
to normal byte register operation */
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MC145572
MOTOROLA