MC145572PB Freescale Semiconductor, MC145572PB Datasheet - Page 46

• Manufacturer Part Number: MC145572PB
• Manufacturer: Freescale Semiconductor

Specifications of MC145572PB

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Not Compliant

4–10
4.3.6
4.3.7
NR5: IDL2 Data Control Register
This register contains controls for the IDL2 interface. More IDL2 controls are in Registers BR6, BR7,
and OR0 – OR9. All bits are cleared on Software Reset (NR0(b3)) or Hardware Reset (RESET). See
Figures 4–4 and NO TAG in Register BR6 description for clarification regarding the precedence of
the swap and blocking functions listed in this register.
Block B1
When this bit is 1 and the IDL2 Invert (BR7(b4)) is 0, the B1 channel is forced to transmit 1s on the
IDL2 interface. When IDL2 Invert (BR7(b4)) is 1, 0s are transmitted in the B1 timeslot. Data received
on the B1 channel from the IDL2 interface is still transmitted normally through the U–interface. The
B1 designator on this bit always refers to the IDL2 interface. Therefore, even if bit Swap B1/B2
(NR5(b0)) is 1, data in the first B channel timeslot on the IDL2 interface is the data that is blocked.
Block B2
When this bit is 1 and the IDL2 Invert (BR7(b4)) is 0, the B1 channel is forced to transmit 1s on the
IDL2 interface. When IDL2 Invert (BR7(b4)) is 1, 0s are transmitted in the B2 timeslot. Data received
on the B2 channel from the IDL2 interface is still transmitted normally out of the U–interface. The
B2 designator on this bit always refers to the IDL2 interface. Therefore, even if bit Swap B1/B2
(NR5(b0)) is 1, data in the second B channel timeslot on the IDL2 interface is the data that is blocked.
Swap B1/B2
When this bit is 1, the IDL2 interface performs a swap of the B channels from the U–interface to the
IDL2 interface and from the IDL2 interface to the U–interface.
R6: eoc Data Register
This register is 12 bits long to match the length of the eoc message. Refer to Tables 4–5 and 4–6
to see how the eoc bits in this register map to the superframe. Operation of Register R6 depends
on the setting of the eoc control bits in BR9(b7:b6) and BR14(b6). This register is double buffered
for read and write operations.
In the default mode (BR14(b6)) is 0, R6 performs as a read–only/write–only register. Data that is read
from R6 by the external microcontroller is the eoc message that the Superframe Deframer stores
according to the eoc Control register (BR9(b7:b6)). Data that is written to R6 is stored in a latch
contained in the Superframe Framer and is subsequently transmitted beginning on the next transmit
eoc frame boundary. The Superframe Framer latches are set to 1s on hardware or software resets.
The Superframe Update Disable register, NR2(b1), has no effect on this register.
When BR14(b6) is set to 1, the Superframe Framer register that contains the transmit eoc message
bits becomes a read/write register. Therefore, the data that is written to the Superframe Framer may
be read back through R6. In this mode, the received eoc message is not available.
R6
NR5
b11
ro/wo
eoc
a1
Reserved bit b3 should be set to 0 at all times to maintain future compatibility.
Freescale Semiconductor, Inc.
b10
ro/wo
eoc
a2
For More Information On This Product,
Reserved
b3
ro/wo
eoc
b9
a3
Go to: www.freescale.com
rw
ro/wo
eoc
dm
b8
MC145572
ro/wo
eoc
b7
i1
Block B1
b2
CAUTION
ro/wo
eoc
b6
i2
rw
eoc
ro/wo
b5
i3
ro/wo
eoc
b4
Block B2
i4
b1
ro/wo
eoc
b3
i5
rw
ro/wo
eoc
b2
i6
Swap B1/B2
ro/wo
eoc
b1
i7
b0
MOTOROLA
eoc
ro/wo
b0
i8
rw