MC145572PB Freescale Semiconductor, MC145572PB Datasheet - Page 159

• Manufacturer Part Number: MC145572PB
• Manufacturer: Freescale Semiconductor

Specifications of MC145572PB

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Not Compliant

MOTOROLA
9.4
9.5
GCI 2B+D MODE PROGRAMMING EXAMPLE
This example shows how to program the MC145572 when the GCI 2B+D format is selected instead
of IDL 8– and 10–bit modes. See Section 5.4.3 for a description of the GCI 2B+D mode.
Procedure GCI2B+Dinit();
/*
PURPOSE:
INITIAL CONDITIONS:
Timeslot assignment:
When the DCL clock frequency = 4.096MHz there are 8 possible 32–bit GCI timeslots. In this
example we will program the MC145572 to transmit and receive in the 4th GCI timeslot.
*/
BEGIN
NR0(b3) <–
NR0(b3) <–
BR10(b0) <–
OR5
OR6(3)
OR10(b0) <–
END;
BLOCK ERROR RATIO CALCULATION USING
This example shows how to use the MC145572 febe and nebe counters to calculate a BLock Error
Ratio (BLER). The BLER is a useful measure of the channel quality as well as a measure of the
far–end and near–end receiver’s performance. Using a timed interrupt, the procedures BLER_init and
BLER_ISR determine the BLER by calculating the number of far–end and near–end block errors that
occurred in the last 100 superframes. By subtracting the value of the febe/nebe counters read during
an interrupt from the value read in the previous interrupt, the error count over a specific time interval
can easily be determined.
The MC145572 has febe and nebe status bits, as well as febe and nebe counters. BR3 contains
the status bits, BR4 is the febe counter and BR5 is the nebe counter. When a febe or nebe is
detected, the status bit is set and the counters are incremented. Section 7.5 describes the operation
of the febe/nebe bits in detail. The MC145572 adds a febe/nebe counter rollover feature which
was not available in the MC145472. When this feature is enabled, the febe/nebe counters will
rollover from $FF to 00 instead of saturating at $FF. The interrupt period of this example has been
set to 1.2 seconds to guarantee that the febe/nebe counters do not roll over more than once
between interrupts.
Since the superframe period is 12 ms, 100 superframes will be transmitted or received in 1.2 se-
conds. The 1.2–second interrupt can easily be implemented using the timer function on any Motorola
MC68HC05 series microcontroller. For greater accuracy, the BLER generated at each interrupt can
be summed over longer periods of time.
By reading BR4 and BR5 once per second it is easy to modify the above procedure to calculate error
seconds and error free seconds.
Program GCI timeslot in IDL–2 GCI 2B+D data format
MC145572 configured for IDL–2 slave mode
DCL clock rate = 4.096 MHz
<–
<–
1;
0;
1;
03;
1;
0;
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/* Assert software reset. Only required at power–up initialization.*/
/* De–assert software reset. Only required at power–up initialization.*/
/* Select Init Group Overlay registers.*/
/* Select the 4th GCI timeslot */
/* Enable 4th GCI timeslot */
/* Timeslot initialization over. Deselect overlay registers and return
to normal byte register operation */
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MC145572
febe
/
nebe
COUNTERS
9–11