MC145572PB Freescale Semiconductor, MC145572PB Datasheet - Page 170

• Manufacturer Part Number: MC145572PB
• Manufacturer: Freescale Semiconductor

Specifications of MC145572PB

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Not Compliant

10–8
10.7.4
IDL2 Slave Long Frame Sync, 8- and 10-Bit Formats
NOTES:
Ref. No.
1. FSR or FSX occurs on average every 125 s. FSX and FSR/FSC must occur every 125 s with a maximum instantaneous
2. FSR or FSX should be asserted for at least two DCL clock cycles and at most eight DCL clock cycles.
3. In IDL 8– and 10–bit formats, TSEN is valid during the B1, B2, and D channel timeslots. TSEN will be aligned with data on
4. In IDL Slave mode, DCL may be any frequency that is a multiple of 8 kHz and is between 256 kHz and 4.096 MHz inclusive.
40
41
42
43
44
45
46
47
48
49
50
51
52
53
phase titter of
the D out pin.
FSR or FSX Period
FSR or FSX High Before the Falling Edge of DCL (FSR or FSX
Setup Time)
FSR or FSX High After the Falling Edge of DCL (FSR or FSX
Hold Time)
FSR or FSX Low Before the Falling Edge of DCL
Delay From Rising Edge of FSR to Low–Z and Valid Data on
D out
Delay From Rising Edge of DCL to Data Valid on D out
Delay From Rising Edge of DCL to High–Z on D out
Delay From Rising Edge of FSR to TSEN Low
Delay From Falling Edge of DCL to TSEN High
DCL Clock Period
DCL Pulse Width High
DCL Pulse Width Low
Data Valid on D in Before Falling Edge of DCL (D in Setup Time)
Data Valid on D in After Falling Edge of DCL (D in Hold Time)
Freescale Semiconductor, Inc.
30 s.
For More Information On This Product,
Go to: www.freescale.com
Parameter
MC145572
Min
125
244
25
25
25
—
—
—
—
45
45
25
25
5
1953
Max
30
30
30
30
30
55
55
—
—
—
—
—
—
% of DCL
% of DCL
Period
Period
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MOTOROLA
s
Note
1
2
2
2
3
4