MC145572PB Freescale Semiconductor, MC145572PB Datasheet - Page 16

• Manufacturer Part Number: MC145572PB
• Manufacturer: Freescale Semiconductor

Specifications of MC145572PB

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Not Compliant

1–2
1.3
1.4
Appendix G, Performance , shows graphs of typical line interface circuit performance.
Appendix H, Test and Debug, gives test and debug information on high impedance digital output
mode, control of transmit signals, and characterization of the pullable crystal.
Appendix I, Glossary of Terms and Abbreviations, contains terms found in this and other Motorola
publications concerned with Motorola Semiconductor Products for Communications.
Appendix J, Standards Bodies, gives a listing of major standards bodies, with contact information.
Every effort has been made to make this a complete and easy to use document; however, contact
your local sales office or the factory applications staff if you require any further assistance.
Information regarding the generic 2B1Q U–interface requirement is readily available in standards docu-
ments such as ANSI T1.601–1992; and therefore, has not been included in this document. The U–inter-
face equipment designer will find the ANSI document to be a useful reference.
FEATURES
Key features of the MC145572 U–interface transceiver include:
REVISIONS
This revision (Rev. 3) of the MC145572/D data book uses change bars to indicate significant changes
or additions to the book with respect to Rev. 2. All references below pertain to MC145572/D, Rev. 3.
The following is a list of sections, figures, and tables with changes.
Sections:
1.1
1.4
Single Chip 2B1Q Echo Cancelling Adaptively Equalized Transceiver
Conforms to ANSI T1.601–1992, Integrated Services Digital Network (ISDN)–Basic Access
Interface for Use on Metallic Loops for Application on the Network Side of the NT (Layer 1
Specification), American National Standards Institute
Compliant to ETSI ETR 080
Warm Start Capability
NT Synchronizes To and Operates With 80 kHz
Supports Master, Slave, and Slave–Slave Timing Modes
On–Chip FIFOs for Transmit and Receive Directions
2B+D Customer Data Provided by the Industry Standard IDL
GCI
Timeslot Assigner
Control, Status, and Extended Maintenance Functions Provided through the SCP
Microprocessor Bus Compatible Parallel Port Available as Pin Selectable Option
On–Chip Conformance with Activation and Deactivation as Specified in ANSI T1.601
Automatic Handling of Basic Maintenance Functions
Automatic Internal Compliance with the Embedded Operations Channel (eoc) Protocol as Speci-
fied in the American National Standard
Complete Set of Loopbacks for Both the IDL– and U–Reference Point Directions
Pin Selectable for LT or NT Applications
On–Chip 2.5 V Transmit Driver Meeting 1992 Requirement
8 kHz Reference Frequency in LT Mode
High Performance CMOS Process Technology
5 V Power Supply
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
MC145572
32 ppm Received Signal from LT
MOTOROLA