MC145572PB Freescale Semiconductor, MC145572PB Datasheet - Page 42

• Manufacturer Part Number: MC145572PB
• Manufacturer: Freescale Semiconductor

Specifications of MC145572PB

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Not Compliant

4–6
4.3.2
2. The external microcontroller sets the Activation Request bit, (NR2(b3)).
3. This bit is reset to 0.
When this bit is 0, the U–interface transceiver is not permitted to enter power–down mode. The U–
interface transceiver has warm start capability regardless of the state of this bit.
Absolute Power–Down
When this bit is 1, the U–interface transceiver enters its Absolute Power–Down mode, the equivalent
of a software reset. All clocks except the Phase Locked Loop (PLL) subsystem used in the LT mode
are shut off when this bit is set to 1. In NT mode, the oscillator is turned off. All internal bias currents
are turned off and the transmit drivers are high impedance. After setting this bit back to 0, the internal
circuits resume full power. After this bit is cleared, the Software Reset bit must be set to 1 for approxi-
mately 1 ms while the internal clocks stabilize. Absolute Power–Down may also be aborted by a Hard-
ware Reset (RESET). During Absolute Power–Down, NR0 is the only register that may be written
to. Setting this bit clears all coefficients and forces the transceiver to activate in cold start mode during
the next activation procedure.
Return to Normal
This bit is used to return maintenance functions to their normal operating state. When set to 1, the
crc Corrupt bit (BR8(b3)) and all of the loopback control bits in BR6 are cleared.
NR1: Activation Status Register
This register contains device activation status. All bits are cleared on Software Reset (NR0(b3)) or
Hardware Reset (RESET). If any bit in this register changes from 0 to 1, or if Linkup, Superframe
Sync, or Transparent/Activation in Progress change from 1 to 0, an IRQ3 (NR3(b3)) is generated.
The IRQ3 interrupt is cleared by reading NR1.
Linkup
This bit is set when the U–interface transceiver has completed an activation up to the point where
full–duplex operation of the U–interface has been established. For the ANSI T1.601–1992 defined
activation to be completed, the act bit in the M4 maintenance bits must still be exchanged. However,
from purely a transmit/receive point of view, the U–interface is operational when Linkup is 1. Linkup
will remain set until one of four things happens:
1. Receive framing is lost or severely in error, and remains so, for 480 ms.
2. While operating in the NT mode, receive framing is lost after Deactivate Request is set in NR2(b2),
3. While operating in the LT mode, the Deactivate Request bit (NR2(b2)) is set.
4. A hardware or software reset occurs.
See D Channel Interrupt below for operation of this bit when D channel access has been enabled
by setting BR10(b1).
or Verified dea (BR3(b1)) becomes a 1 during M4 Control mode 0,0 (BR9(b5:b4)).
NR1
When access to the D channel via register OR12 is enabled, NR1 indicates a D channel inter-
rupt by setting all four status bits to 1s. Reading OR12 clears the special code (1111) from
NR1 but does not affect any updates in activation status. So, if there has been a change in
activation status, an interrupt is still queued up even though the D channel interrupt has been
cleared.
Freescale Semiconductor, Inc.
For More Information On This Product,
LINKUP
b3
Go to: www.freescale.com
r0
MC145572
INDICATION
ERROR
b2
NOTE
ro
SUPERFRAME
SYNC
b1
ro
TRANSPARENT
ACTIVATION IN
PROGRESS
b0
MOTOROLA
ro