MC145572PB Freescale Semiconductor, MC145572PB Datasheet - Page 150

• Manufacturer Part Number: MC145572PB
• Manufacturer: Freescale Semiconductor

Specifications of MC145572PB

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Not Compliant

9–2
9.2.1
channel interrupt service routine, NTISR1, is also provided in Section 9.2.1. Procedure NTINIT2 in
Section 9.2.2 initializes the MC145572 for non–automatic eoc operation when in the NT mode. The
corresponding sample high level embedded operations channel interrupt service routine, NTISR2,
is also provided in Section 9.2.2. Procedure LTINIT1 in Section 9.3 initializes the MC145572 when
it is operated in LT mode.
The sample initialization and operation examples given here are to be used as a guide only. All data
written to or read from registers is in hexadecimal. User eoc, M channel, and activation handlers are
implementation specific. In this example, M4 channel is initialized to $77 in NT mode and $7F in LT
mode. The $77 in NT mode indicates act bit not asserted, ps1 and ps2 status normal, NT1 not in
test mode, warm start capability, and all ANSI T1.601–1988 reserved bits set to 1s. The $7F in LT
mode indicates the act bit is not asserted, the dea bit is not asserted, and all ANSI T1.601–1988
reserved bits set to 1s. The bits in the M5 and M6 channels are all initialized to 1s and R6 is initialized
to $1FF (Return to Normal) when in the LT mode. It is not necessary to initialize R6 in the NT mode
since the specific eoc handler used will respond to the incoming eoc messages from the LT.
When the U–interface transceiver first activates after a cold or warm start, the febe and nebe count-
ers, BR4 and BR5, should be cleared by the software. Provision must be made so these two registers
are not cleared if there has been a temporary dropout of data transparency or loss of frame sync; i.e.,
only clear these counters upon initial activation. When a temporary loss of frame sync or signal occurs
without the U–interface transceiver going to the full reset state, it is important that the febe and nebe
count values accurately reflect CRC errors during this time. A reasonable time to clear the febe and
nebe counters is when the M4 channel act bits are first exchanged after initial activation from warm
or cold start. If the febe and nebe counters in the NT are cleared when linkup occurs, it is possible to
get febe counts due to the LT transceiver not having completed its activation sequence.
NT Automatic eoc Mode Initialization and Activation
The MC145572 provides a mode for trinal checking and automatic invoking of NT1 eoc functions as
defined in ANSI T1.601–1992. In this mode, the external microcontroller does not need to perform
trinal checking, decoding, and implementation of eoc messages. The M4 trinal consecutive check
mode is used in this example. Note that only the act, dea, and uoa M4 bits are verified three consec-
utive times. The following three code segments: NTACT1(), NTINIT1(), and NTISR1() configure the
MC145572 in the above modes and are an example implementation of an NT initiated full activation
in an NT1. The NT1 initiates activation of the U–interface only when requested to do so by the termi-
nal equipment (TE) or upon cycling of NT1 power.
An initialization and activation procedure for an NT1 follows. A suggested interrupt service routine
outline, NTISR1, is also given.
Procedure NTACT1();
/*
PURPOSE:
The activation procedure NTACT1 resets the U–interface transceiver, calls the initializa-
tion routine NTINIT1, sets activate request, and waits for interrupts.
*/
BEGIN
NR0(b3) <–
NR0(b3) <–
CALL NTINIT1();
NR2(b3) <–
Wait for interrupt;
Other code;
END;
1;
0;
1;
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/* Assert software reset. Only required
/* De–assert software reset. Only required at power–up
/* Set activation request bit.*/
/* Wait for result of Activation */
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at power–up initialization/
initialization/
MC145572
MOTOROLA