MC145572PB Freescale Semiconductor, MC145572PB Datasheet - Page 64

• Manufacturer Part Number: MC145572PB
• Manufacturer: Freescale Semiconductor

Specifications of MC145572PB

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Not Compliant

4–28
4.4.15
Fast DFE/ARC Beta
This bit controls the betas for the DFE and ARC. When set to 1, the DFE and ARC adapt at their
highest rate.
Clear All Coefficients
When set to 1, the coefficients in the DFE, ARC, TEC, and MEC are cleared and the elastic buffer
is reset. The timing offset between the receive and transmit clocks is not altered by setting this bit.
EPI 10:3
These are the least significant bits of the EPI register within the CPU. The EPI register in the CPU
takes on different meanings, depending on the current activation state. This EPI register is updated
once per frame. The EPI 18:11 bits are in Register BR12. EPI 2:0 are not available to the external
microcontroller.
BR14: Test Register
This register is used for setting various diagnostic modes. This register is cleared on a Hardware Reset
(RESET) or Software Reset (NR0(b3)). When all of these bits are 0, the register map is in the default
mode.
ro/wo to r/w
When this bit is set to 1, all of the write–only registers, except BR15A, become read/write registers
for diagnostic purposes. A bit that is normally read–only will not be available when this bit is set to
1. Setting this bit to 1 has no effect on BR15A(b4:b0); they remain write–only bits at all times.
Framer–to–Deframer Loopback
This bit enables the Superframe Framer to Superframe Deframer Loopback mode when it is 1. The
transmit drivers are off in this mode.
When this bit is set to 1, the Superframe Framer generates its tones (10 kHz and 40 kHz) using
Enable CLKs
When set to 1, this bit enables the SYSCLK, EYEDATA, RxBCLK, TxBCLK, and TxSFS pins. Note
that BR15A(b3) must also be set to 1 for the TxSFS output to be enabled.
1 Tones
1 quats instead of the default of
BR14
SYSCLK, EYEDATA, RxBCLK, TxBCLK, and TxSFS pin functionality can be modified by
the setting of bits in OR8 and OR9.
Reserved
b7
Freescale Semiconductor, Inc.
rw
Reserved bits b7, b5, b2, and b1 must be set to 0 at all times.
For More Information On This Product,
ro/wo
to r/w
b6
Go to: www.freescale.com
rw
Reserved
MC145572
b5
3 quats.
rw
Framer–to–
CAUTION
Deframer
Loop
NOTE
b4
rw
1 Tones
b3
rw
Reserved
b2
rw
Reserved
b1
rw
MOTOROLA
Enable
CLKs
b0
rw