MC145572PB Freescale Semiconductor, MC145572PB Datasheet - Page 123

• Manufacturer Part Number: MC145572PB
• Manufacturer: Freescale Semiconductor

Specifications of MC145572PB

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Not Compliant

Freescale Semiconductor, Inc.
The crc Corrupt mode bit, OR9(b2), modifies the operation of crc Corrupt, BR8(b3). When OR9(b2)
is a 1, the operation of the crc Corrupt bit, BR8(b3), is modified so that a corrupt crc is transmitted
only to the end of the current U–interface superframe. Then BR8(b3) is cleared to a 0. If it is desired
to corrupt the transmitted crc again, then BR8(3) must be set to a 1 again. This is very useful for
digital loop carrier applications, since software does not have to clear BR8(b3) in order to guarantee
a one–to–one correspondence between crc received from the digital loop carrier system and crcs
transmitted onto the U–interface. For digital loop carrier applications, BR9(b1) is set to a 1 if it is
desired to have end–to–end performance monitoring. The outgoing febe should be updated at the
same time that the outgoing M4 channel register is updated. This update should be done for every
superframe.
7.7
MAINTENANCE CHANNEL INTERRUPTS AND UPDATES
This section provides details on when interrupts are generated and when the internal Superframe
Framer reads maintenance channel registers to include their contents in the outgoing transmitted
superframe. This information is particularly useful when designing LUNT and LULT line cards for digital
loop carrier systems. The basic frames and Quat positions are numbered as in the ANSI T1.601 specifi-
cation. A Quat is the ANSI T1.601 term for the symbols transmitted over the U–interface. Basic frames
are numbered from 1 through 8. The Quats in each basic frame are numbered from 1 through 120.
The M4, M5/M6, and eoc maintenance subchannels can be used for signalling in proprietary applica-
tions. When the M4 or M5/M6 subchannels are configured to update on every received frame in the
subchannel, the update interval is 12 ms or once every superframe. The receive data interrupt for
the M5/M6 subchannel occurs at the end of basic frame 4. The receive data interrupt for the M4 channel
occurs at the end of the superframe or basic frame 8. See Figures 7–1, 7–2 and 7–3, and register
BR9 description for more details.
When the eoc subchannel is configured to update on every received eoc frame, the update interval
is 6 ms, or twice each superframe. The eoc receive data interrupt can occur at the end of basic frame
4 or at the end of basic frame 8. See register description for BR9 for more details.
The receive and transmit registers for the maintenance channels are double buffered. Figure 7–2 indi-
cates where maintenance channel registers are updated from the superframe received at NT. Fig-
ure 7–2 also indicates the points where the U–interface transceiver transfers data from the mainte-
nance channel registers into the transmitted superframe when the MC145572 is configured for NT
mode. Figure 7–3 indicates where maintenance channel registers are updated from the superframe
received at the LT end of the loop. Figure 7–3 also indicates the points where the U–interface transceiv-
er transfers data from the maintenance channel registers into the transmitted superframe when the
MC145572 is configured for LT mode.
For digital loop carrier applications, maintenance channel registers R6, BR1, and BR3 must be pro-
grammed to update on every received frame. Do not use trinal or dual consecutive checking. The
reason for this, is intermediate nodes need to do local processing of the eoc messages and must
transmit the messages upstream or downstream on a frame–by–frame basis. See explanations for
Byte register 9. Note that the eoc maintenance subchannel R6 is updated with a new received eoc
message twice each superframe. The MC145572 should be configured so that interrupts are generated
when BR1, BR3, and R6 are updated. See explanations for Nibble registers 3 and 4. The interrupt
for BR3 (IRQ0) may not need to be enabled, since BR3 is updated at the same time as R6 at the
end of a superframe. When an interrupt occurs, data can be read from the appropriate maintenance
channel register (BR1, BR3, or R6) and transmitted over the digital loop carrier system. At this time,
the maintenance channel data that has been received from the digital loop carrier system can be written
to the registers for the outgoing superframe (BR0, BR2, or R6).
If the M4 channel and eoc interrupts are enabled to occur on the reception of every frame, it is possible
for the software to determine if eoc interrupt has occurred at the end of basic frame 4 or at the end
of basic frame 8. When eoc interrupt occurs at the end of basic frame 4, eoc interrupt status bit,
NR3(b2), is set and M4 channel interrupt status bit, NR3(b1), is clear assuming that M4 channel regis-
ter, BR1, was read immediately following the previous M4 channel interrupt. When eoc interrupt and
M4 interrupts occur at the end of basic frame 8, both NR3(b2) and NR3(b1) are set.
The MC145572 does not provide any direct mechanism whereby an external microcontroller can
determine when registers, for outgoing maintenance data, can be updated. This timing must be
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