MC145572PB Freescale Semiconductor, MC145572PB Datasheet - Page 37

• Manufacturer Part Number: MC145572PB
• Manufacturer: Freescale Semiconductor

Specifications of MC145572PB

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Not Compliant

MOTOROLA
MCU MODE REGISTER DESCRIPTION REFERENCE
4.1
INTRODUCTION
This chapter describes all of the MC145572 U–interface transceiver control and status registers avail-
able via the Serial and Parallel Control Ports. Tables 4–1 through 4–3 contain Register Maps and
Section 4.2.1 contains a Register Index. See Section 4.3 for detailed descriptions of each register.
The internal registers of the MC145572 are used when the device is in MCU mode. When in GCI
mode, MCU/GCI = 0, the MC145572 is controlled via the C/I and Monitor channels and it is not neces-
sary to access the registers in normal applications.
The MC145572 provides a PCP interface mode that provides access to all control registers. See Sec-
tion 5.3.2 for more information on the use of the PCP interface.
The register map for the MC145572 is nearly identical to that for the MC145472 after a hardware
or software reset. Reserved bits in the MC145472 register map have been redefined to permit access
to new registers in the MC145572. Most software developed for the MC145472 will work for the
MC145572 without modifications.
The MC145572 SCP interface is pin–for–pin identical to that of MC145474/75 and MC145574 S/T–
interface transceivers. Using the same interface as the MC145474/75 provides a common interface
for applications utilizing both the MC145572 and the MC145474/75 and for applications that can use
either device, such as line cards or terminal equipment.
In addition to being pin–for–pin compatible, the architecture of the register map and the SCP interface
is nearly identical to that of the MC145474/75. This simplifies the code development effort and mini-
mizes device driver code size for the microcontroller.
For complete information on the operation of Control interfaces, see Section 5.3.
R6
NR0
NR1
NR2
NR3
NR4
NR5
Table 4–1. Nibble Registers and R6 Map (NR0 – NR5; R6) — See Section 4.3
b11
eoc
a1
Activation Request
Software Reset
Enable IRQ3
Reserved
b10
Linkup
eoc
a2
IRQ3
Freescale Semiconductor, Inc.
b3
For More Information On This Product,
eoc
b9
a3
Go to: www.freescale.com
eoc
dm
Deactivation Request
b8
Power–Down Enable
Error Indication
Enable IRQ2
MC145572
Block B1
IRQ2
b2
eoc
b7
i1
eoc
b6
i2
Absolute Power–Down
eoc
Superframe Update
b5
i3
Superframe Sync
Enable IRQ1
Block B2
Disable
IRQ1
b1
eoc
b4
i4
eoc
b3
i5
Transparent Activation
eoc
b2
i6
Customer Enable
Return to Normal
Enable IRQ0
Swap B1/B2
in Progress
IRQ0
b0
eoc
b1
i7
4
eoc
b0
i8
4–1