MC145572PB Freescale Semiconductor, MC145572PB Datasheet - Page 210

• Manufacturer Part Number: MC145572PB
• Manufacturer: Freescale Semiconductor

Specifications of MC145572PB

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Not Compliant

C–2
C.4
C.5
Figure C–1 shows a suggested board layout for a two layer board. This drawing is not done to scale.
Trace vias are shown. Depending on the application, other pins may need to be connected to V DD
or V SS . All bypass capacitors should be located as close as possible to the V SS /V DD pins. The
suggested layout shows the power feed to the MC145572 coming from a common point. This is
important in a two layer implementation. The 10 F electrolytic capacitor is recommended to filter
out any ripple or noise that may be on the board in a two layer application. Even though the
MC145572 has very high power supply rejection, good power supply decoupling is recommended.
If a four layer board with full power and ground planes is used, the V DD and V SS pins can be con-
nected directly to the appropriate plane by vias.
OSCILLATOR LAYOUT GUIDELINES
All traces must be as short as possible to reduce stray capacitance and inductance. The traces to
XTAL in and XTAL out must be kept as short as possible with minimal width to keep stray capacitance
less than 1 pF. Other digital signals should not be routed near the crystal traces. Any passive compo-
nents for the oscillator or PLL should have short leads and should be soldered to the PC board.
Wherever possible the layout should be symmetrical, so the stray capacitances from each pin of the
crystal to ground are equal.
When a four layer board is used, do not route ground or power plane material underneath the
20.48 MHz crystal oscillator circuitry. This is to minimize parasitic capacitances between the
20.480 MHz oscillator traces and the power or ground plane. Excessive parasitic capacitance between
the traces and power/ground planes decreases the pull range of the 20.48 MHz oscillator.
2B1Q INTERFACE GUIDELINES
The line interface into and out of the device is differential, implying symmetry. It is recommended that
the layout of the 2B1Q interface be as symmetrical as possible to avoid any imbalances to this circuit.
Do not run any digital traces through the line interface region of the printed circuit board.
5. Use short, wide, low inductance traces to connect all of the V SS ground pins together and,
6. Use short, wide, low inductance traces to connect all of the V DD power supply pins together
7. Motorola recommends that a four layer board be used. It is possible to use a two layer board
8. The 20.48 MHz crystal must be located as close as possible to the MC145572 package. This
with one trace, connect all of the V SS ground pins to the power supply ground. Depending on
the application, a double sided PCB with a V SS ground plane under the device connecting all
of the digital and analog V SS pins together would be a good grounding method. A multi–layer
PCB with a ground plane connecting all of the digital and analog V SS pins together would be
the optimal ground configuration. These methods will result in the lowest resistance and the
lowest inductance in the ground circuit. This is important to reduce voltage spikes in the ground
circuit resulting from the high speed digital current spikes. Suppressing these voltage spikes
on the integrated circuit is the reason for multiple V SS ground leads.
and, with one trace, connect all of the V DD power supply pins to the 5–V power supply. De-
pending on the application, a double sided PCB with V DD bypass capacitors to the V SS ground
plane under the device, as described in item 5 above, may complete the low impedance cou-
pling for the power supply. For a multi–layer PCB with a power plane, connecting all of the
digital and analog V DD pins to the power plane would be the optimal power distribution method.
The integrated circuit layout and packaging considerations for the 5–V V DD power circuit are
essentially the same as for the ground circuit.
but special care must be taken. See Figure C–1.
is required to minimize parasitic capacitances between crystal traces and ground.
Freescale Semiconductor, Inc.
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MC145572
MOTOROLA