MC145572PB Freescale Semiconductor, MC145572PB Datasheet - Page 69

• Manufacturer Part Number: MC145572PB
• Manufacturer: Freescale Semiconductor

Specifications of MC145572PB

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Not Compliant

MOTOROLA
4.5.9
Internal Analog Loopback
When this bit is set to 1, the analog loopback path is inside the MC145572. Default after any reset
is 0 or external analog loopback path.
Line Connect
When this bit is 1, the U–interface line can remain connected during analog loopbacks. When this
bit is 0, the line must be disconnected. Default after any reset is 0.
TSEN DCH Enable
This bit enables TSEN when D channel data is present on the D out or DCH out pins. When the
timeslot assigner is enabled, the TSEN signal is active during the timeslot which D channel data is
transferred.
IDL2 Rate 2
In the IDL2 mode, when IDL2 rate 2 is set to 1, the IDL2 clock (DCL) rate is 512 kHz. IDL2 clock
speed (see Register BR7) is ignored when this bit is set to 1. In full GCI mode, as a master in the
NT mode, the DCL clock rate is selected using the pin input (see CLKSEL description in Section 3.3.4).
This bit also sets the clock frequency on FREQREF or FREF out when in NT Slave mode.
IDL2 Long Frame Mode
While operating as an IDL2 master, this bit controls whether the FSR and FSX operate in Long Frame
or Short Frame mode. If this bit is 1, both FSR and FSX operate in Long Frame mode. As an IDL2
slave, the MC145572 determines the mode based on the length of FSR. See Section 5.4.2.
crc Corrupt Mode
This bit changes the operating mode of the input control bit crc Corrupt in register BR8. When crc
Corrupt mode is set to 1, the crc Corrupt input is used to only corrupt one outgoing superframe crc.
When crc Corrupt mode is set to 0, the crc Corrupt behaves as it did in the MC145472, unaligned
to the transmit superframe, and continues to affect the crc data until explicitly reset.
febe/nebe Rollover
This bit changes the operating mode of the febe and nebe counter registers BR4 and BR5. When
febe / nebe rollover is set to 1, the febe and nebe counter registers do not saturate at all 1s, but
instead, rollover from $FF to $00. When febe / nebe rollover is set to 0, the febe and nebe counter
registers behave just as they do in the MC145472.
M4 Trinal Mode
This bit changes the operating mode of the persistence checking performed on the act, dea, sai,
and uoa bits in the deframer. When M4 Trinal mode is set to 1, the checked M4 bits must be valid
for three consecutive superframes before asserting Verified act, or Verified dea, etc. When M4 Trinal
mode is set to 0, the checked M4 bits behave as they did in the MC145472, only checking them as
configured in BR9(b5,b4). When operating in full GCI mode, the MC145572 performs trinal checks
on the received M4 channel act, dea, sai, and uoa bits (see Table 4–11).
OR8: Configuration Register 2
This register is used to control the dump/restore operation, SFAX and SFAR outputs, and three–state
enable for off–chip bus drivers. After a hardware or software reset, all bits default to 0 to maintain
MC145472/MC14LC5472 compatibility.
OR8
Mode 1
D/R
b7
Freescale Semiconductor, Inc.
rw
For More Information On This Product,
Mode 0
D/R
b6
Reserved bit b2 must be set to 0 at all times.
Go to: www.freescale.com
rw
Output
Enable
SFAX
b5
MC145572
rw
FREQREF
CAUTION
Output
Enable
b4
rw
Enable
TSEN
BCH
b3
rw
Reserved
b2
rw
Enable
SFAX/
SFAR
b1
rw
D Channel
Enable
Port
b0
rw
4–33