MC145572PB Freescale Semiconductor, MC145572PB Datasheet - Page 54

• Manufacturer Part Number: MC145572PB
• Manufacturer: Freescale Semiconductor

Specifications of MC145572PB

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Not Compliant

4–18
GCI IN1/OUT1
This is a read–only/write–only bit. The write only portion, OUT1, is cleared by hardware and software
resets. In full GCI mode, entered by holding the pin MCU/GCI low, the state of OUT1 is driven onto
a GCI mode dedicated output pin. When read (again, provided the MC145572 is in full GCI mode),
bit IN1 reflects the state of a GCI mode dedicated input pin. These pins may be used for any purpose
in a GCI application. See Chapter 3, Device Description , for more information. GCI command LTD1
when active in LT mode or NTD1 when active in NT mode, sets OUT1 high.
IDL2 Invert
When set to 1, this bit forces the IDL2 interface to invert every bit just before it is transmitted on the
D out pin and invert every bit that is received on D in .
IDL2 Free Run
When set to 0, this bit forces the DCL and FSR/FSX outputs to run continuously when in the IDL2
Master mode. When this bit is 1, the DCL and FSR/FSX stop when the U–interface transceiver is
deactivated. DCL and FSR/FSX will start operating when Superframe Sync in NR1(b1) becomes 1
and halts when the U–interface transceiver enters the ANSI T1.601 defined “Tear Down” state.
IDL2 Speed
This bit selects the DCL clock speed in the IDL2 Master mode. When this bit is 0, the clock rate is
2.56 MHz. A 1 selects a rate of 2.048 MHz. This bit also sets the output clock rate for FREQREF
or FREF out when in NT Slave mode. Also, see the description for OR7(b4).
IDL2 M/S Invert
When this bit is 1, it inverts the polarity of the IDL2 Master/Slave pin. When this bit is 0 and IDL2
Master is set high, the U–interface transceiver operates in the IDL2 Master mode.
IDL2 8/10
This bit reorders the sequence of 2B + D data presented in the IDL2 data transfer. The two possible
transfer sequences are shown in Figures 4–3 and 4–4. A 1 selects the 8–bit mode and a 0 selects
the 10–bit mode. In the 8–bit mode, the two B channels are provided sequentially, followed by the
two D channel bits. In the 10–bit mode, one D channel bit follows each B channel byte. The ability
to swap the B channels, (NR5(b0)), applies to both of these modes. For further information about
the IDL2 interface, see Section 5.4.
If timeslot assignment mode is enabled via OR6 b(7), b(6), or b(5), then the IDL2 8/10
control bit is ignored and B channel and D channel data is placed according to OR0 – OR5.
If GCI electrical mode is selected by setting OR6(b3) to a 1, the IDL2 interface transfers
only 2B + D data in the GCI timeslot locations as programmed in OR5(b2:b0).
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MC145572
NOTE
MOTOROLA