MC145572PB Freescale Semiconductor, MC145572PB Datasheet - Page 51

• Manufacturer Part Number: MC145572PB
• Manufacturer: Freescale Semiconductor

Specifications of MC145572PB

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Not Compliant

MOTOROLA
4.4.7
OR7(b1) is cleared, BR5 counts to $FF and does not roll over. This is the default configuration after
any reset to maintain MC145472 compatibility.
BR6: Loopback Control Register
This register contains the loopback controls. For normal (no loopback) operation, bits b7:b5 and b3:b1
of BR6 should be 0. BR6 is cleared by a Software Reset (NR0(b3)), Hardware Reset (RESET), or
when the Return to Normal bit (NR0(b0)) is set. When a bit is set to 1, the appropriate loopback is
enabled. This register is replaced by Register OR6 when BR10(b0) = 1.
Bits b7 through b4, inclusive, are not set when the MC145572 is operating in the automatic eoc mode.
U–Loop B1
This bit selects a loopback on the B1 channel toward the U–interface.
U–Loop B2
This bit selects a loopback on the B2 channel toward the U–interface.
U–Loop 2B+D
This bit selects a loopback on the B1, B2, and D channels toward the U–interface.
U–Loop Transparent
This bit selects whether the loopback toward the U–interface should be handled transparently or not.
This transparency selection applies to all channels that are selected for loopback to the U–interface.
IDL2–Loop B1
This bit selects a loopback on the B1 channel toward the IDL2 interface. This bit operates in all IDL2
and GCI modes.
IDL2–Loop B2
This bit selects a loopback on the B2 channel toward the IDL2 interface. This bit operates in all IDL2
and GCI modes.
IDL2–Loop 2B+D
This bit selects a loopback on the B1, B2, and D channels toward the IDL2 interface. When this bit
is set to 1, the IDL2–loop B1 and IDL2–loop B2 bits are ignored. This bit operates in all IDL2 and
GCI modes.
IDL2–Loop Transparent
This bit selects whether the loopback toward the IDL2 interface should be handled transparently or
not. This transparency selection applies to all channels that are selected for loopback to the IDL2
interface.
BR6
BR5
Counter 7
U–Loop
nebe
B1
b7
b7
Freescale Semiconductor, Inc.
rw
rw
For More Information On This Product,
Counter 6
U–Loop
nebe
b6
b6
B2
Go to: www.freescale.com
rw
rw
Counter 5
U–Loop
2B + D
nebe
b5
b5
MC145572
rw
rw
Counter 4
U–Loop
Trans–
parent
nebe
b4
b4
rw
rw
Counter 3
IDL–Loop
nebe
b3
b3
B1
rw
rw
Counter 2
IDL–Loop
nebe
b2
b2
B2
rw
rw
Counter 1
IDL–Loop
2B + D
nebe
b1
b1
rw
rw
Counter 0
IDL–Loop
Trans–
parent
nebe
b0
b0
rw
rw
4–15