MC145572PB Freescale Semiconductor, MC145572PB Datasheet - Page 172

• Manufacturer Part Number: MC145572PB
• Manufacturer: Freescale Semiconductor

Specifications of MC145572PB

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Not Compliant

10–10
10.8
GCI TIMING
NOTES:
Ref. No.
1. The FSC pulse is normally two DCL clock periods wide.
2. The FSC pulse is only one DCL clock period wide at the start of a superframe. Every 96th FSC pulse marks the start of
3. To mark the beginning of a superframe (i.e., to flag the 2B+D data of the current frame as the first data in the transmitted
4. In GCI Master mode, the MC145572 will output a 512 kHz or 2.048 MHz clock as selected by CLKSEL.
5. In GCI Slave mode, DCL may be any frequency that is a multiple of 512 kHz and is between 512 kHz and 8.192 MHz.
6. The duty cycle of DCL is between 45% and 55% when operated in Master Timing mode. This duty cycle is guaranteed for
59a
59b
53
54
55
56
57
58
60
61
62
63
64
65
66
67
68
69
70
a superframe.
superframe) the FSC pulse should be only one DCL clock period wide. If the FSC pulse is not modulated as such the
MC145572 will randomly chose an FSC frame as the first to be transmitted.
all DCL clocks, except the clock that is used for making timing adjustments, in order to maintain synchronization with the
received signal when operating in NT mode. In NT Master mode, the MC145572 conveys timing adjustments over the DCL
clock of the device. This is done by adding or subtracting a single 20.48 MHz clock period of 48 ns to the high phase of DCL
clock on two successive GCI frames, once per U–interface basic frame. The total adjustment is 96 ns distributed over the
two frames. When DCL is configured for 2.048 MHz, the adjustment occurs during clock pulse number 249 after FSC. The
count starts at clock pulse 0 for the DCL clock immediately coincident with FSC being driven high. When DCL is configured
for 512 kHz the adjustment occurs during DCL pulse number 59. It is important to remember this when programming the
GCI timeslot, since it is possible for data to be transferred during the clock period where the timing adjustment is being made
and this may effect setup and hold times for other components in a system.
Delay From Rising Edge of DCL to FSC Output High
Delay From Rising Edge of DCL to FSC Output Low (Normal Frame)
Delay From Rising Edge of DCL to FSC Output Low (Superframe
Marker)
FSC Input High Before the Falling Edge of DCL (FSC Setup Time)
FSC Input High After the Falling Edge of DCL (FSC Hold Time —
Superframe Marker)
FSC Input High After the Falling Edge of FSC (FSC Hold Time —
Normal Frame)
DCL Clock Period Master Mode
DCL Clock Period Slave Mode
DCL Pulse Width High
DCL Clock 249 Pulse Width High
DCL Clock 59 Pulse Width High
DCL Pulse Width Low
DCL Fall Time
DCL Rise Time
Delay From Rising Edge of FSC to Low–Z and Valid Data on D out
Delay From Rising Edge of DCL to Data Valid on D out
Delay From Rising Edge of DCL High–Z on D out
Data Valid on D in Before Rising Edge of DCL
Data Valid on D in After Rising Edge of DCL
Delay From Rising Edge of FSC to TSEN Low
Delay From Rising Edge of DCL to TSEN High
Freescale Semiconductor, Inc.
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Parameter
MC145572
2.048 MHz
2.048 kHz
512 kHz
512 kHz
Min
488
122
878
210
160
825
—
—
—
25
25
25
45
—
—
25
25
—
—
5
5
5
1953
1953
1074
1120
Max
265
315
30
30
30
55
15
15
30
30
30
30
30
—
—
—
—
—
% of DCL
Period
Unit
MOTOROLA
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note
1
2
1
3
4
5
6