MC145572PB Freescale Semiconductor, MC145572PB Datasheet - Page 67

• Manufacturer Part Number: MC145572PB
• Manufacturer: Freescale Semiconductor

Specifications of MC145572PB

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Not Compliant

MOTOROLA
4.5.4
4.5.5
4.5.6
4.5.7
OR3: D in B1 Timeslot Register
Programmed the same way as OR0. This register controls when the B1 timeslot is input from the
D in pin. After a hardware or software reset, all bits default to 0 to maintain MC145472/MC14LC5472
compatibility.
OR4: D in B2 Timeslot Register
Programmed the same way as OR0. This register controls when the B2 timeslot is input from the
D in pin. After a hardware or software reset, all bits default to 0 to maintain MC145472/MC14LC5472
compatibility.
OR5: D in D and GCI Timeslot Register
Programmed similar to OR2. This register controls when the D timeslot is input from the D in pin.
After a hardware or software reset, all bits default to 0 to maintain MC145472/MC14LC5472 com-
patibility.
GCI Slot (2:0)
In IDL2 mode, if OR6 b(3) is set to indicate GCI 2B+D operation, b(2:0) is used to program the GCI
timeslot. These bits are treated like the S2, S1, and S0 pins in Full GCI mode. See Table 3–7 for
timeslot assignment.
OR6: Timeslot and GCI Control Register
This register is used to enable the timeslot assigner and select GCI 2B+D data format when in IDL2
mode. After a hardware or software reset, all bits default to 0 to maintain MC145472/MC14LC5472
compatibility.
OR3
OR4
OR5
OR6
Setting b7, b6, or b5 will put the MC145572 in Timeslot Assigner mode. In Timeslot Assign-
er mode, the IDL2 8/10 mode bit in BR7(b0) is ignored and data is placed according to
values programmed in OR0 – OR5.
TSA B1
Enable
b7
b7
b7
b7
Freescale Semiconductor, Inc.
rw
For More Information On This Product,
TSA B2
Enable
b6
b6
b6
b6
Go to: www.freescale.com
rw
Enable
TSA D
b5
b5
b5
b5
MC145572
D in B1 Channel Timeslot Bits (7:0)
D in B2 Channel Timeslot Bits (7:0)
rw
D in D Channel Timeslot Bits (7:0)
GCI Select
M4 – BR0
NOTE
b4
b4
b4
b4
rw
GCI Mode
Enable
b3
b3
b3
b3
rw
rw
Reserved
S2 Bit
b2
b2
b2
b2
rw
Reserved
GCI Slot
S1 Bit
b1
b1
b1
b1
rw
Reserved
S0 Bit
b0
b0
b0
b0
rw
rw
rw
rw
4–31