MC145572PB Freescale Semiconductor, MC145572PB Datasheet - Page 124

• Manufacturer Part Number: MC145572PB
• Manufacturer: Freescale Semiconductor

Specifications of MC145572PB

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Not Compliant

Freescale Semiconductor, Inc.
derived from the interrupts generated when the receive maintenance subchannel registers are
updated. Figures 7–2 and 7–3 show the appropriate timings. It is possible to configure the TxSFS/
SFAX/S0 pin as SFAX and use the pulse to generate a 12–ms periodic interrupt. Note though that
SFAX indicates the 2B+D frame in the IDL2 interface that will be transmitted onto the first 2B+D
position in basic frame 1 of the U–interface superframe. Due to the internal FIFOs, it is not possible
to guarantee a fixed time between SFAX and the location of the superframe marker on the U–inter-
face.
At the NT end, the ANSI T1.601 specification requires a turnaround delay of 60
2 quats. The
MC145572 has a 60–quat turnaround time. This means that the transmitted Superframe Sync word
occurs 60 quats later than the received Superframe Sync word. From an interrupt service routine
point of view, updating BR0, BR2, and R6, the worst case time should be assumed to be 60 quats
+ 117 quats = 177 quats, or 2.2 ms. The system software designer should allow extra margin to be
safe. A quat is 12.5 s in duration.
At the LT end of the loop, the received Superframe Sync word is 60 – 2 + 8 quats later than the
transmit Superframe Sync word. The 2–quat uncertainty comes from the ANSI T1.601 specification
for NT turnaround time of 60
2 quats on a 0 length loop. The + 8 figure includes worst case propa-
gation delay on an 18,000–foot loop. From an interrupt service routine point of view, the worst case
assumption is that the receive Superframe Sync word occurs 68 quats after the transmitted Super-
frame Sync word. For example, from Figure 7–3, the time between when R6 is updated with the
receive eoc data and when R6 must be updated with the transmitted eoc data, can be calculated
as follows: 117 – 68 = 49 quats or 612.5 s. The system software designer should leave extra margin
to be safe.
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