MC145572PB Freescale Semiconductor, MC145572PB Datasheet - Page 66

• Manufacturer Part Number: MC145572PB
• Manufacturer: Freescale Semiconductor

Specifications of MC145572PB

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Not Compliant

4–30
4.5.1
4.5.2
4.5.3
4.5
OVERLAY REGISTERS
Table 4–3 shows the registers on MC145572 that overlay the standard byte registers. The SCP address
for the overlay registers is the same as the address for the standard byte register set. The overlay
registers are substituted for the standard registers, when at least one of BR7(b7) or BR10(b2, b1,
b0) is set to 1. BR15A was implemented in MC145472, but the other registers are new to MC145572.
BR15A was modified on MC145572 from MC145472, to change the 15.36 MHz and 20.48 MHz clock
outputs to default to enabled. In order to maintain code–compatibility with MC145472, the bits were
moved from BR15A to the overlay registers. To disable these clocks, OR9(b2, b1, b0) can be set to
1s.
Overlay registers OR0 – OR5 are used for defining the timeslot assignment when the IDL2 interface
is put into Timeslot Assigner mode by setting one or more of the bits TSA B1 Enable, TSA B2 Enable,
or TSA D Enable, found in Overlay register OR6. Timeslots are two DCL clocks in width and are num-
bered starting from 0.
Overlay register OR5 also is used to define the GCI timeslot when the bit GCI Mode Enable is asserted
in Overlay register OR6. The remainder of the bits in Overlay registers OR6 – OR9 are explained
following Table 4–3.
All bits in the overlay registers are reset to 0 on hardware and software resets. The overlay registers
are hidden after a hardware or software reset. They can be accessed when BR10(b0) is set to 1.
OR0: D out B1 Timeslot Register
This register controls when the B1 timeslot appears on the D out pin. After a hardware or software
reset, all bits default to 0 to maintain MC145472/MC14LC5472 compatibility.
OR1: D out B2 Timeslot Register
Programmed the same way as OR0. This register controls when the B2 timeslot appears on the
D out pin. After a hardware or software reset, all bits default to 0 to maintain MC145472/
MC14LC5472 compatibility.
OR2: D out D Timeslot Register
Programmed the same way as OR0. This register controls when the D timeslot appears on the
D out pin. After a hardware or software reset, all bits default to 0 to maintain MC145472/
MC14LC5472 compatibility.
OR0
OR1
OR2
b7
b7
b7
Freescale Semiconductor, Inc.
For More Information On This Product,
b6
b6
b6
Go to: www.freescale.com
MC145572
b5
b5
b5
D out B1 Channel Timeslot Bits (7:0)
D out B2 Channel Timeslot Bits (7:0)
D out D Channel Timeslot Bits (7:0)
b4
b4
b4
b3
b3
b3
b2
b2
b2
b1
b1
b1
MOTOROLA
b0
b0
b0
rw
rw
rw