MC145572PB Freescale Semiconductor, MC145572PB Datasheet - Page 103

• Manufacturer Part Number: MC145572PB
• Manufacturer: Freescale Semiconductor

Specifications of MC145572PB

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Not Compliant

MOTOROLA
INTERFACE
IDL2 OR GCI
CONTROL
INTERFACE
5.6.1
CONTROL PORT
CONTROLLER
INTERFACE &
PROCESSOR
CONTROLLER
AUTOMATIC
ACTIVATION
D CHANNEL
AUTOMATIC
REGISTER
U-Interface Loopback
A U–interface loopback configuration is shown in Figure 5–34. As the shaded portion of the block
diagram shows, this loopback mode exercises virtually the entire U–interface transceiver. The 2B1Q
symbols are received from the far–end transmitter, recovered, passed through the IDL2 interface block,
and transmitted back to the far–end receiver.
The four most significant bits of BR6 control the U–interface loopback modes. The loopback occurs
in the IDL2 interface section of MC145572. Data appearing at the D in pin is ignored (i.e., not
transmitted onto the U–interface). By setting U–Loop Transparent (BR6(b4)), to a 1, the loopback
is made transparent and the D out pin is enabled, permitting transfer of recovered data onto the IDL2
interface. When U–Loop Transparent (BR6(b4)), is reset to a 0, the B and D channels at the D out
pin are forced to idle 1s when a loopback is enabled. If IDL2 Invert (BR7(b4)) is set to a 1, then the
B and D channels at the D out pin idle at all 0s.
The U–interface loopback is selected by setting one or more of U–loop B1, U–loop B2, or U–loop
2B+D (BR6(b7:b5)) to a 1. To enable loopback of B1 channel data to the U–interface, U–loop B1
(BR6(b7)) is set to a 1. To enable loopback of B2 channel data to the U–interface, U–loop B2 (BR6(b6))
is set to a 1. To enable loopback of 2B+D data to the U–interface, U–loop 2B+D (BR6(b5)) is set to
a 1. The 2B+D loopback overrides any B1 or B2 channel loopback that has been enabled. When
the Automatic eoc Processor in the MC145572 is enabled, the logical OR of loopback modes enabled
by the Automatic eoc Processor and loopback modes selected in BR6 are enabled. As a result, the
external microcontroller can always enable a loopback whether the U–interface transceiver is oper-
ated with the Automatic eoc Processor or not.
When the U–interface transceiver is operating without the Automatic eoc Processor, loopback modes
can be disabled by setting to a 1 and then resetting to a 0, the Return to Normal bit, NR0(b0). This
clears all bits in BR6 and clears the crc Corrupt Control bit, BR8(b3). The loopback modes can also
be cleared by resetting the appropriate bits in BR6 to a 0.
AND GCI
FIFO
FIFO
eoc
Rx
Tx
IDL2
2B + D
2B + D
Figure 5–34. U–Interface Loopback Block Diagram
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MC145572
OSCILLATOR / PLL
CRYSTAL
DAC
EQUALIZER
RECOVERY
FEEDBACK
DECISION
SLICER
TIMING
Tx FILTER
CANCELLER
FILTER
ECHO
ADC
Rx
-
XTAL in
XTAL out
DRIVER
Tx
INTERFACE
EXTERNAL
TxP
TxN
RxP
RxN
LINE
U INTERFACE
5–31