MC145572PB Freescale Semiconductor, MC145572PB Datasheet - Page 33

• Manufacturer Part Number: MC145572PB
• Manufacturer: Freescale Semiconductor

Specifications of MC145572PB

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Not Compliant

MOTOROLA
RxBCLK/DCH out /D7/CLKSEL
SYSCLK/SFAR/TSEN/S1
DCH in : D Channel Data In
DCH in is the D channel port serial input. It is enabled by setting D channel port enable
in Init Group register OR8(b0).
D6: Data 6
In Parallel Control Port mode, this pin functions as bit 6 of the data bus.
FREF out : GCI Mode Locked Frequency Output
In full GCI mode, operating as a slave, this pin provides 2.048 MHz or 512 kHz synchro-
nized clock output as selected by CLKSEL. When the MC145572 is configured as a GCI
timing master, FREF out does not provide a clock since the clock is present on DCL. It is
not necessary to set any register bits to enable this output in GCI slave mode.
RxBCLK: Transmit Baud Clock Output
This 80 kHz clock indicates the timing of the received 2B1Q bauds. Control bits BR14(b0)
or BR15A(b0) must be set to logic 1 to enable this signal.
DCH out : D Channel Data Out
DCH out is the D channel port serial output. It is enabled by setting D channel port enable
in Init Group register OR8(b0).
D7: Data 7
In Parallel Control Port mode, this pin functions as bit 7 of the data bus.
CLKSEL: Clock Select
When operating as a GCI timing master in full GCI mode, CLKSEL selects between
512 kHz and 2.048 MHz for DCL. CLKSEL = 1 selects 2.048 MHz.
When operating as a GCI timing slave in full GCI–NT mode, CLKSEL selects between
phase locked 512 kHz and 2.048 MHz clocks appearing at FREF out .
SYSCLK: System Clock Output
System Clock Output is a 10.24 MHz clock that is used to clock Eye Pattern Data. Control
bits BR14(b0) or BR15A(b0) must be set to a 1 to enable this signal. See Appendix D
for applications information concerning this pin.
SFAR: Superframe Alignment Receive
SFAR provides a superframe alignment output signal in the NT and LT modes. This signal
is only available when the MC145572 is in MCU mode. Setting OR8 (b1) enables this
output. This signal is one MCU clock wide and occurs during the DCL clock following FSR.
See Section 5.4.7. This pulse indicates the first 2B+D frame received from a U–interface
superframe.
TSEN: Open–Drain Buffer Enable Output
TSEN is an open–drain buffer enable output, used for enabling a bus driver to buffer TDM
data out from the MC145572 onto a PCM highway. When the MC145572 is configured
for MCU mode, TSEN is active during the B1, B2, and D channel timeslots, regardless
of where they occur. When the MC145572 is configured for GCI 2B + D electrical–only
interfacing while in MCU mode, TSEN is active during the B1, B2, and D channel timeslots
only. TSEN is also available when the MC145572 is configured for timeslot assigner opera-
tion. When a separate D channel serial port option is enabled, TSEN is active only during
the B1 and B2 channel timeslots. This pin is enabled when OR7(b5) = 1 or OR8(b3) = 1.
S1: GCI Mode Slot Selection 1
In full GCI mode, this pin is an input for the timeslot selection, S0 – S2.
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MC145572
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