MC145572PB Freescale Semiconductor, MC145572PB Datasheet - Page 63

• Manufacturer Part Number: MC145572PB
• Manufacturer: Freescale Semiconductor

Specifications of MC145572PB

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Not Compliant

MOTOROLA
4.4.14
Hold Activation State
When this bit is set to 1, the activation controller is held in the current state until either a Load Activation
State (b5) or a Step Activation State (b4) is performed.
Big Jump Select
When this bit is 1, timing phase jumps will be made in four–unit increments. When this bit is 0, timing
phase jumps will be made in one–unit increments.
Force Linkup
When this bit is set to 1, the internal status is forced to be that of full–duplex operation. Note that
the CPU is still operating according to the activation state as read in BR11. However, loopbacks and
maintenance operations may be performed at the Superframe Framer/Deframer level with full data
transparency.
EPI 18:11
These are the most significant bits of the EPI register within the CPU. The EPI register in the CPU
takes on different meanings, depending on the current activation state. This EPI register is updated
once per frame. The EPI 10:3 bits are in Register BR13. EPI 2:0 are not available to the external
microcontroller.
BR13: Echo Canceller Test Register
This register contains several items that control the internal operation of the U–interface transceiver
echo canceller. These bits are cleared on a Hardware Reset (RESET) or Software Reset (NR0(b3)).
Note that none of the control bits in this register affect the operation of the chip unless the Activation
Control Steer bit in BR12(b7) is set to 1. This register is replaced by OR13, when BR10(b2) = 1.
Enable MEC Updates
When set to 0, this bit freezes the current coefficients of the Memory Echo Canceller (MEC).
Accumulate EC Output
When this bit is set to 1, the results of all three echo cancellers (MEC, Transversal Echo Canceller
(TEC), and Infinite Impulse Response Echo Canceller (IIREC)) are included in the process of recover-
ing the received symbol.
Enable EC Updates
When set to 0, this bit freezes the current coefficients of the TEC and IIREC echo cancellers.
Fast EC Beta
This bit controls the echo canceller beta constant. A 1 instructs the echo canceller to adapt at its fastest
rate.
Accumulate DFE Output
When 0, this bit forces the output from the Decision Feedback Equalizer (DFE) convolution to 0 and
the symbol storage elements of the DFE will set to alternating 1. When this bit is 1, the DFE convolu-
tion is included in the process of recovering the received symbol.
Enable DFE Updates
When set to 0, this bit freezes the DFE coefficients and the Adaptive Reference Control (ARC) tap.
BR13
Updates
Enable
EPI 10
MEC
b7
Freescale Semiconductor, Inc.
wo
ro
For More Information On This Product,
Accumu-
late EC
Output
EPI 9
b6
Go to: www.freescale.com
wo
ro
Enable EC
Updates
EPI 8
b5
MC145572
wo
ro
Fast EC
EPI 7
Beta
b4
wo
ro
Accumu-
late DFE
Output
EPI 6
b3
wo
ro
Updates
Enable
EPI 5
DFE
b2
wo
ro
DFE/ARC
EPI 4
Beta
Fast
b1
wo
ro
Clear All
Coeffi-
cients
EPI 3
b0
wo
ro
4–27