MC145572PB Freescale Semiconductor, MC145572PB Datasheet - Page 99

• Manufacturer Part Number: MC145572PB
• Manufacturer: Freescale Semiconductor

Specifications of MC145572PB

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Not Compliant

MOTOROLA
5.4.8.1
5.4.8.2
5.4.8.3
5.4.8
IDL2 2B+D Data Alignment to U-Interface Superframe
The MC145572 provides signals that indicate the relationship between data transferred over the IDL2
interface and where that data is positioned in the U–interface superframe. In IDL2 short frame and
long frame operation, the SFAX and SFAR pins are used to indicate the IDL2 2B+D data frame that
corresponds to the first 2B+D block in basic frame 1 of the U–interface superframe. This feature is
enabled by setting OR8(b1), SFAX/SFAR ENABLE to a 1 when the MC145572 is configured for IDL2
operation.
SFAX provides superframe alignment timing for data transmitted onto the U–interface. It is active dur-
ing the IDL2 frame that corresponds to the 2B+D data transmitted at the start of basic frame 1 on the
U–interface. In NT mode, SFAX is always an output. In LT mode, SFAX defaults to an input and is
used to force alignment of the outgoing superframe, as well as indicating transfer of the first 2B+D
frame of U–interface basic frame 1 into D in of the IDL2 interface. When in LT mode, setting OR8(b5),
SFAX Output Enable to a 1, configures SFAX as an output and indicates transfer of the first 2B+D
frame of U–interface basic frame 1 into D in of the IDL2 interface. When SFAX is not enabled as an
input, the MC145572 selects the starting point of the transmitted superframe when in LT mode.
SFAR provides superframe alignment timing for data received from the U–interface. It is active during
the IDL2 frame that outputs 2B+D data from the MC145572 that arrived at the start of basic frame
1 on the U–interface. SFAR is always an output when enabled.
When configured for GCI 2B+D operation, the FSC signal is used to indicate superframe alignment.
The superframe alignment signal(s) occur once every 96 IDL2 or GCI frames. Since frames are
125 s in duration, this corresponds to 12 ms (96 x 125 s), which is the duration of a U–interface
superframe.
IDL2 SHORT FRAME MODE SUPERFRAME ALIGNMENT
In IDL2 short frame format, SFAX and SFAR indicate the IDL2 frame corresponding to the first 2B+D
block in the U–interface superframe by pulsing high for one DCL clock time. This occurs immediately
following the IDL2 frame syncs FSX and FSR (see Figures 5–31a and 5–32a). When configured as an
input, SFAX must be driven high for the DCL clock period immediately following FSX and it is sampled
on the falling edge of DCL.
IDL2 LONG FRAME MODE SUPERFRAME ALIGNMENT
In IDL2 long frame format, SFAX and SFAR indicate the IDL2 frame corresponding to the first 2B+D
block in the U–interface superframe by pulsing high for the duration of FSX and FSR, respectively
(see Figures 5–31b and 5–32b).
GCI 2B+D MODE SUPERFRAME ALIGNMENT
When configured for IDL2 GCI 2B+D data format, OR6(b3) = 1, the MC145572 uses the FSC signal
to indicate superframe alignment. Inputs on SFAX are ignored.
In LT mode, when MC145572 is configured as an IDL2 slave, the FSC pin is used to force alignment
of the transmitted U–interface superframe. Normally, the FSC pulse is two DCL clocks in duration.
The transmit superframe alignment is set by driving FSC with a one DCL clock wide pulse once every
96 GCI frames. The 2B+D data read into the D in pin, corresponding to the single clock wide FSC,
is the first 2B+D frame transmitted onto the U–interface. If superframe alignment is not input to FSC,
the MC145572 aligns the outgoing U–interface superframe alignment (see Figure 5–33).
When configured for Master mode and either LT or NT operation, reception of the first 2B+D data
of the U–interface superframe is indicated by outputting a FSC pulse that is one DCL clock wide.
This happens once every 96 GCI frames.
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MC145572
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