MC145572PB Freescale Semiconductor, MC145572PB Datasheet - Page 94

• Manufacturer Part Number: MC145572PB
• Manufacturer: Freescale Semiconductor

Specifications of MC145572PB

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Not Compliant

5–22
5.4.6
Timeslot Assigner
The MC145572 has a timeslot assigner that can be used when configured for MCU mode. The timeslot
assigner is enabled when one or more of OR6(b7, b6, or b5) are set to a 1. The starting timeslot(s)
are programmed into Overlay registers OR0 – OR5. The B1, B2, and D channels are each indepen-
dently programmable for both transmit and receive directions.
Timeslots are each two DCL clocks wide. Timeslot numbering starts from timeslot 0. Timeslot 0
occurs during the first two DCL clocks following FSX or FSR. DCL clocks are numbered starting from
0. Clock number 0 is the first DCL clock after the frame sync pulse FSX or FSR. Since FSX and FSR
can occur at different times, DCL clocks are counted referenced to either FSX or FSR depending on
which data direction is being configured. The timeslot number is calculated by counting the DCL
clocks after the appropriate frame sync where it is desired to place the start of the B or D channel
timeslot. This DCL count is divided by two and the resulting value is written to the appropriate timeslot
register.
The D channel data is always two contiguous DCL clocks or one timeslot in duration. B channel data
is always eight contiguous DCL clocks or four timeslots in duration. B channel timeslots may be pro-
grammed to start in any timeslot, though in normal applications, B channel timeslots are programmed
to start on every fourth timeslot or eighth DCL clock. Data is transferred between MC145572 and the
IDL2 interface only during B1, B2, or D channel timeslots that are enabled. When a B or D channel
timeslot is disabled, data appearing at the D in pin is ignored and the D out pin is high impedance.
Table 5–5 details the timeslot assigner registers in the overlay register set. See Figures 5–27 and
5–28 for timeslot format examples.
The register programming for Figure 5–27 is as follows:
The register programming for Figure 5–28 is as follows:
The register programming for Figure 5–29 is as follows:
Enabling the timeslot assigner overrides all other IDL2 frame formats with the exception of GCI 2B+D.
In GCI 2B+D data format, OR5 bits 2:0 are used to select the active GCI channel.
When the D channel port is enabled, the corresponding D channel timeslot is not enabled on the IDL2
interface. Instead, the D channel data is transferred over the D channel port referenced to FSR as
programmed in Overlay registers OR2 or OR5. This is also true when IDL2 GCI 2B+D mode has been
enabled. The D out pin of the IDL2 interface is high impedance and data at D in is ignored. Figure 5–29
gives an example of D channel port operation when the timeslot assigner is enabled.
OR0
OR1
OR2
OR3
OR4
OR5
OR6
OR0 = $04
OR1 = $0B
OR2 = $01
OR0 = $00
OR2 = $0D
OR3 = $04
OR5 = $01
OR0 = $00
OR1 = $0B
OR2 = $08
B1 Enable
TSA
Freescale Semiconductor, Inc.
For More Information On This Product,
B2 Enable
TSA
Table 5–5. Timeslot Assigner Registers
Go to: www.freescale.com
OR3 = $00
OR4 = $08
OR5 = $0D
OR6 = $50
OR7 = $20
OR8 = $08
OR3 = $00
OR4 = $0B
OR5 = $08
D Enable
D in D Channel Timeslot Bits (7:0) and GCI Slot (2:0)
TSA
MC145572
D out B1 Channel Timeslot Bits (7:0)
D out B2 Channel Timeslot Bits (7:0)
D out D Channel Timeslot Bits (7:0)
D in B1 Channel Timeslot Bits (7:0)
D in B2 Channel Timeslot Bits (7:0)
GCI Select
M4 – BR0
OR6 = $E0
OR7 = $20
OR8 = $08
OR6 = $E0
OR7 = $00
OR8 = $09
GCI Mode
Enable
Reserved
Reserved
MOTOROLA
Reserved