MC145572PB Freescale Semiconductor, MC145572PB Datasheet - Page 78

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MC145572PB

Manufacturer Part Number
MC145572PB
Description
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MC145572PB

Number Of Line Interfaces
1
Control Interface
HDLC
Lead Free Status / Rohs Status
Not Compliant

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5–6
5.3.1.1
NIBBLE REGISTER OPERATION
The 4–bit nibble registers are accessed via an 8–bit SCP interface operation, as shown in Figure 5–3
for a write operation and Figure 5–4 for a read operation. The first bit of the transfer on SCPRx is
a read/write (R/W) bit, indicating the purpose of the operation. This is followed by a 3–bit address
field (A2:A0), which specifies nibble address 0 through nibble address 5. (Nibble addresses 6 and
7 have other purposes, which are described later.) For a write operation, the 4–bit data word (D3:D0)
follows. For a read operation, the 4–bit data word (D3:D0) follows on the SCPTx pin.
SCPCLK
SCPCLK
SCPEN
SCPEN
SCPRx
SCPTx
SCPRx
SCPTx
R/W
R/W
Freescale Semiconductor, Inc.
Figure 5–3. SCP Nibble Registers 0 – 5, Write Operation
Figure 5–4. SCP Nibble Registers 0 – 5, Read Operation
For More Information On This Product,
A2
A2
A1
A1
Go to: www.freescale.com
A0
A0
D3
D3
MC145572
D2
D2
D1
D1
D0
D0
HIGH IMPEDANCE
HIGH IMPEDANCE
DON'T CARE
DON'T CARE
DON'T CARE
DON'T CARE
MOTOROLA

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