MC145572PB Freescale Semiconductor, MC145572PB Datasheet - Page 40

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MC145572PB

Manufacturer Part Number
MC145572PB
Description
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MC145572PB

Number Of Line Interfaces
1
Control Interface
HDLC
Lead Free Status / Rohs Status
Not Compliant

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4–4
Activation (continued)
GCI
IDL2
Interrupt
Loopbacks
nebe
Step Activation State — BR12(b4)
Superframe Sync — NR1(b1)
Superframe Update Disable — NR2(b1)
Timer Disable — BR11(b0)
Timer Expire — BR11(b0)
Transparent — NR1(b0)
Verified act — BR3(b2), BR9(b5:b4)
Verified dea — BR3(b1), BR9(b5:b4)
Deactivation
IN/OUT — BR7(b6:b5)
GCI Mode Enable — OR6 (b3)
Timeslot Assigner
D out B1 Timeslot — OR0
D out B2 Timeslot — OR1
D out D Timeslot — OR2
D in B1 Timeslot — OR3
D in B2 Timeslot — OR4
D in D Timeslot — OR5
TSA Enable — OR6 (b7:b5)
8–Bit/10–Bit Mode — BR7(b0)
Block B1 — NR5(b2)
Block B2 — NR5(b1)
Customer Enable — NR2(b0)
Free Run — BR7(b3)
Invert — BR7(b4)
Loopbacks — See Loopbacks
Master/Slave Invert — BR7(b1)
Speed — BR7(b2)
Swap B1/B2 — NR5(b0)
B1 IDL2 Timeslot Enable — OR6(b7)
B2 IDL2 Timeslot Enable — OR6(b6)
D IDL2 Timeslot Enable — OR6(b5)
IDL2 Long Frame Mode — OR7(b3)
IDL2 Rate — OR7(b4)
Enable — NR5
Status — NR3
Framer–to–Deframer Loop — BR14(b4)
IDL2–Loop 2B + D — BR6(b1)
IDL2–Loop B1 — BR6(b3)
IDL2–Loop B2 — BR6(b2)
IDL2–Loop Transparent — BR6(b1)
Match Scrambler — BR8(b2)
Receive Window Disable — BR8(b1)
U–Loop 2B + D — BR6(b5)
U–Loop B1 — BR6(b7)
U–Loop B2 — BR6(b6)
U–Loop Transparent — BR6(b4)
Open Feedback Switch — OR9(b6)
Analog Loopback — OR9(b5)
Computed — BR3(b3)
Control — BR9(b1)
Counter — BR5
febe/nebe Rollover — OR7(b2)
Request — NR2(b2)
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
MC145572
Diagnostics (continued)
eoc
febe
Maintenance
Mode
Superframe Framer
Fast EC Beta — BR 13(b4)
Force Linkup — BR12(b0)
Freq Adapt — BR15A(b7)
Jump Disable — BR15A(b6)
Mask — BR15(b4:b0)
ro/wo to r/w — BR14(b6)
Superframe Detect — BR3(b0)
Select Dump Access — BR10(b2)
Select DCH Access — BR10(b1)
D Channel Access Overlay — OR12
Dump/Restore Access Overlay — OR13
Control — BR9(b7:b6)
act — BR3(b2)
Message — R6
Control — BR9(b1)
Counter — BR4
Input — BR2(b4), BR9(b1)
Received — BR3(b4)
febe/nebe Rollover — OR7(b2)
act — BR3(b2)
crc Corrupt — BR8(b3)
dea — BR3(b1)
eoc — See eoc
febe — See febe
M4 Trinal Mode — OR7(b0)
M4 Control — BR9(b5:b4)
M4 Send — BR0
M4 Received — BR1
M5/M6 Control — BR9(b3:b2)
M50 Received — BR3(b7)
M50 Send — BR2(b7)
M51 Received — BR3(b5)
M51 Send — BR2(b5)
M60 Received — BR3(b6)
M60 Send — BR2(b6)
nebe — See nebe
Return to Normal — NR0(b0)
Superframe Update Disable — NR2(b1)
Verified act — BR3(b2)
Verified dea — BR3(b1)
Absolute Power–Down — NR0(b1)
NT/LT Invert Mode — BR8(b0)
NT/LT Mode — BR8(b0)
Power–Down Enable — NR0(b2)
Software Reset — NR0(b3)
GCI 2B+D Mode — OR6(b3)
Frame Control — BR8(b6:b4)
Frame State — BR8(b7:b4)
Frame Steering — BR8(b7)
MOTOROLA

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