MC145572PB Freescale Semiconductor, MC145572PB Datasheet - Page 120

• Manufacturer Part Number: MC145572PB
• Manufacturer: Freescale Semiconductor

Specifications of MC145572PB

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Not Compliant

7–4
7.6
The current febe count is maintained in BR4. The count in BR4 is incremented only when the re-
ceived febe bit is detected active (0) at the end of the superframe. When OR7(b1) is a 0, the febe
counter does not wrap around when the count reaches $FF. When OR7(b1) is a 1, the febe counter
wraps around and continues counting from 0. Also, BR4 should be reset to 00 after Linkup is detected
during activation. This is done by the external microcontroller writing 00 to BR4. The count is increm-
ented when both Superframe Sync and Linkup in NR1(b1, b3) are set to a 1 and the received febe
bit is a 0. Received febe is available in BR3(b4) and is a 0 when active.
The current nebe count is maintained in BR5. The count in BR5 is incremented only when the Com-
puted nebe bit is detected active (0) at the end of the superframe. The count is also incremented
once per superframe during loss of synchronization, i.e., if Superframe Sync, NR2(b1), drops to a
0 when Linkup, NR2(b3), is set to a 1. When OR7(b1) is a 0, the nebe counter does not wrap around
when the count reaches $FF. When OR7(b1) is a 1, the nebe counter wraps around and continues
counting from 0. Also, BR5 should be reset to 00 after Linkup is detected during activation. This is
done by the external microcontroller writing 00 to BR5. The count is incremented when both Super-
frame Sync and Linkup in NR1(b1, b3) are set to a 1 and when an error is detected in the received
crc. A Computed nebe is active when the received crc does not exactly match the calculated crc
on the received superframe data. The Computed nebe is available in BR3(b3) and is a 0 when a
crc error has been detected.
FORCE CORRUPT
The MC145572 provides a mechanism where the outgoing crc can be corrupted. The transmitted
crc is corrupted when BR8(b3) is set to a 1. The crc corruption is accomplished by inverting the
transmitted crc bits. See Table 7–1. The next two paragraphs are of particular interest to designers
of digital loop carrier system LULT and LUNT type line cards.
In NT mode operation, when it is desired to corrupt the outgoing crc, BR8(b3) should be set at the
end of reception of basic frame 4 and must be cleared at the end of reception of basic frame 8. This
inverts the outgoing crc in transmitted basic frames 4, 5, 6, and 7 of the current transmitted super-
frame. See Figure 7–2. When crc Corrupt mode, OR7(b2), is set to a 1, it is not necessary to clear
BR8(b3), since it is cleared automatically at the end of the transmitted superframe. This guarantees
that the corrupt crc will be transmitted only in the current superframe and that there will be a one–to–
one correspondence between the corrupt crc status received from a digital carrier system and the
corrupt crc transmitted on the U–interface. See Section 7.7.
In LT mode operation, when it is desired to corrupt the outgoing crc, BR8(b3) should be set at the
end of reception of basic frame 8 and must be cleared at the end of reception of basic frame 8. This
inverts the outgoing crc in transmitted basic frames 1 through 8 of the current transmitted super-
frame. See Figure 7–3. When crc Corrupt mode, OR7(b2), is set to a 1, it is not necessary to clear
BR8(b3), since it is cleared automatically at the end of the transmitted superframe. This guarantees
that the corrupt crc will be transmitted only in the current superframe and that there will be a one–to–
one correspondence between the corrupt crc status received from a digital carrier system and the
corrupt crc transmitted on the U–interface. See Section 7.7.
BR8(b3)
0
1
1
Freescale Semiconductor, Inc.
OR9(b2)
Table 7–1. Transmitted crc Configuration
For More Information On This Product,
X
0
1
crc
No effect, transmitted crc is a good crc and far–end transceiver receives
it correctly. This is the default mode after any reset.
Transmitted crc is continuously corrupted by inverting the crc symbols.
This causes the far–end transceiver to detect crc errors. BR8(b3) must be
returned to a 0 to stop the transmission of bad crcs.
Transmitted crc is corrupted only until the end of the current U–interface
superframe. Then BR8(b3) is cleared to 0.
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MC145572
Effect on Transmitted crc
MOTOROLA