MC145572PB Freescale Semiconductor, MC145572PB Datasheet - Page 48

• Manufacturer Part Number: MC145572PB
• Manufacturer: Freescale Semiconductor

Specifications of MC145572PB

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Not Compliant

4–12
4.4.1
4.4.2
4.4
BYTE REGISTERS
BR0: M4 Transmit Data Register
This register contains the M4 bits that are framed and sent by the Superframe Framer. The bits
written to this register are sent out on the next transmit superframe boundary, if Superframe Update
Disable (NR2(b1)) is set to 0. This register is double buffered. All bits are set to 1s following a Hard-
ware Reset (RESET) or Software Reset (NR0(b3)). This register is replaced by Register OR0 when
BR10(b0) = 1.
Table 4–7 shows the definitions of the M4 bits as defined by ANSI T1.601–1992 for the Network to
NT channel and the NT to Network channel.
BR1: M4 Receive Data Register
By reading this register, the external microcontroller obtains a buffered copy of the M4 bits that are
parsed from the received superframe by the Superframe Deframer. The values in the register are
valid when Superframe Sync (NR1(b1)) is 1. See Register BR9(b5:b4) for a description of when the
“read” information is updated and when to write to this register. This register is double buffered. The
receive M4 channel byte can be read at any time during the superframe prior to the next update. It
is recommended that the MPU read this register as soon as possible after an interrupt. Note that
BR14(b6) has no effect on the operation of this register. Bit 0 in Overlay register OR7 selects trinal
checking on M4 act, dea, uoa, sai bits when set to 1. If trinal checking is desired for all bits, then
it must be done in software. This register is replaced by Register OR1 when BR10(b0) = 1. When
OR7(b0) is set, the M4 act, dea, uoa, sai bits must be the same for three superframes before they
are updated in this register.
BR0
BR1
BR0 should not be modified while device is in GCI mode. See OR6(b4).
M40
M40
b7
b7
ro/wo
Freescale Semiconductor, Inc.
[ ] These are bit definitions for the revised ANSI T1.601–1992. In ANSI T1.601–
** These bits are presently reserved by ANSI T1.601–1988 and should be set
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* These bits are defined in Bellcore document TR–NWT000397, Issue 3. When
For More Information On This Product,
set to 0, the LT indicates to the NT that the network will deactivate the loop
between calls.
to 1s.
1988 they were set to 1s.
M41
M4 Bits
M41
b6
b6
M40
M41
M42
M43
M44
M45
M46
M47
ro/wo
Go to: www.freescale.com
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Table 4–7. M4 Bit Definitions
M42
M42
MC145572
b5
b5
ro/wo
rw
Network to NT
CAUTION
M43
M43
b4
b4
[uoa]
[aib]
sco*
act
dea
ro/wo
1**
1**
1**
rw
M44
M44
b3
b3
ro/wo
rw
NT to Network
M45
M45
b2
b2
[sai]
nib*
act
ps1
ntm
cso
ps2
ro/wo
1**
rw
M46
M46
b1
b1
ro/wo
rw
MOTOROLA
M47
M47
b0
b0
ro/wo
rw