MC145572PB Freescale Semiconductor, MC145572PB Datasheet - Page 34

• Manufacturer Part Number: MC145572PB
• Manufacturer: Freescale Semiconductor

Specifications of MC145572PB

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Not Compliant

3–12
3.3.5
3.3.6
2B1Q Line Interface Pins
These pins form the 2B1Q interface of the MC145572 U–interface transceiver. Refer to Appendix
E for information on the line interface. Refer to Appendix B for component sourcing.
Crystal Oscillator and Phase Locked Loop (PLL) Pins
In LT mode, the MC145572 derives its 20.48 MHz master clock from a clock reference using an on–chip
PLL with an 8 kHz clock reference applied to pin FREQREF.
In NT mode, no reference clock is required, since timing is recovered from the line. External circuitry
is the same for both NT and LT modes.
TxSFS/SFAX/S0
TxP and TxN: Transmit Positive and Transmit Negative Outputs
These are the differential analog output pins of the transmit line driver.
RxP and RxN: Receive Positive and Receive Negative Inputs
These are the differential analog input pins to the 2B1Q receiver.
V ref P and V ref N: Reference Voltage Positive and Reference Voltage
Connect a 0.1 F ceramic capacitor between these pins.
FREQREF: Frequency Reference
TxSFS: Transmit Superframe Sync Output
This output pulses high, 8 bauds prior to the transmit sync word separating the first and
second transmitted basic frames in a superframe. Control bits BR14(b0) and BR15A(b3)
must both be set to a 1 to enable this pin. The TxSFS output is coincident with the Tx
Baud Clock.
TxSFS is provided for compatibility to the MC145472, which provides an absolute transmit
superframe reference.
SFAX: Superframe Alignment Transmit
SFAX is the transmit superframe alignment input in the LT mode, or superframe alignment
output in the NT mode. SFAX is enabled by setting SFAX/SFAR Enable in Init Group register
OR8 (b1). SFAX may be configured as an output in LT mode by setting OR8 (b5). See
Sections 4.5.9 and 5.4.7. When GCI 2B+D mode is enabled, MCU/GCI = 1, and OR6(b3)
= 1, the SFAX function is superceded by modulation of the FSC input. This pulse indicates
the first 2B+D IDL frame transmitted onto the U–interface superframe.
S0: Slot Selection 0
In full GCI mode, this pin is an input for the timeslot selection, S0 – S2.
In MCU mode (MCU/GCI pin connected to V DD ), this pin function becomes un-
defined after a hardware or software reset. Most applications do not use any
of the features available at this pin. In such cases, a 10 k
connected between this pin and V SS . In the rare applications that enable any
of the functions available at this pin, the 10 k
This applies to both NT and LT mode operation.
LT Mode: This Schmitt trigger digital input pin accepts the 8 kHz reference frequency
for the analog phase locked loop in LT mode. Typically, this clock can be the same
8 kHz synchronization input as connected to FSR or FSX. For ISDN central office
applications, the frequency applied at this pin should be stable to
Freescale Semiconductor, Inc.
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MC145572
WARNING
resistor may not be required.
resistor must be
5 ppm to meet
MOTOROLA