MC145572PB Freescale Semiconductor, MC145572PB Datasheet - Page 92

• Manufacturer Part Number: MC145572PB
• Manufacturer: Freescale Semiconductor

Specifications of MC145572PB

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Not Compliant

5–20
5.4.4
5.4.5
Master and Slave Mode Operation
The MC145572 can be configured for IDL2 master or IDL2 slave operation independently of LT or
NT configuration. A logic 1 selects IDL2 master operation and a logic 0 selects IDL2 slave operation.
When configured as an IDL2 slave, FSX and FSR can be independently driven by external circuitry.
FSX and FSR must be synchronized to the clock applied to DCL. If there is only a single synchronization
source, the FSR and FSX pins can be tied together and driven from a single source. In Slave mode,
the IDL2 interface can accept an input clock at DCL between 512 kHz and 8.192 MHz.
As an IDL2 master, MC145572 drives FSX and FSR simultaneously, so that the active high time of
each signal coincides with each other. The 2B+D data transfer into D in and out of D out occurs
simultaneously. For applications where only one output synchronization pulse is required, either FSX
or FSR can be used. As an IDL2 master, MC145572 outputs data clocks of 512 kHz, 2.048 MHz,
and 2.56 MHz. The DCL clock rate is programmed by BR7(b2) and OR7(b4). See Table 5–4.
D Channel Port
When operated in MCU mode with SCP enabled, MC145572 can be configured to have a separate
data port for D channel data. The D channel port is available for short frame data format and GCI
2B+D data format. When PCP is used to access the MC145572 register set, the D channel port is
not available, since the pins are assigned to the data bus of the parallel port. The D channel port
is enabled by setting OR8(b0), D Channel Port Enable, to a 1. After a hardware or software reset,
the D channel port is disabled. Figure 5–2 shows an LT mode configuration with D channel port enabled.
The D channel port has three signals: DCH in (D channel data input), DCH out (D channel data output),
and DCHCLK (D channel clock). When the D channel port is enabled, DCHCLK is always a clock
output. The clock is a gated clock, based on whatever is on DCL. The clock occurs whenever the
normal D1 and D2 bits would have occurred during the transfer taking place over D out with respect
to FSR. Internal buffering of the data received on DCH in aligns the data for transmission onto the
U–interface. DCH out does not go high impedance.
When the D channel port is enabled, D channel bits are diverted to the port, and the D out pin on the
IDL2 interface is high impedance during the D bit times. Data bits received at IDL2 interface D in pin
are ignored during the D channel bit times. In timeslot assigner mode, D channel bits are transferred
at the time programmed in register OR2, D out D Channel Timeslot bits. Figures 5–24 through 5–26
show the D channel port timing.
TSEN
D out
DCL
FSC
D in
Freescale Semiconductor, Inc.
B1
For More Information On This Product,
Figure 5–23. IDL2 GCI 2B+D Data Formats
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