MC145572PB Freescale Semiconductor, MC145572PB Datasheet - Page 70

• Manufacturer Part Number: MC145572PB
• Manufacturer: Freescale Semiconductor

Specifications of MC145572PB

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Not Compliant

Freescale Semiconductor, Inc.
D/R Mode (1:0)
These bits control the operating mode of Dump/Restore Access Overlay register OR12. {0,0} sets
the mode for normal dumping and restoring of the internal coefficients via the EYE out interface. {1,0}
permits read access to the arctap. {0,1} permits write access to the arctap. {1,1} should be selected
to perform dump/restore via the IDL2 or GCI interface depending on the state of the MCU/GCI pin.
SFAX Output Enable
When this bit is set to 1 in LT mode, it forces the SFAX pin to be an output. Normally, in LT mode,
SFAX is an input to control the start of the transmit superframe.
FREQREF Output Enable
When this bit is set to 1 in NT mode, it forces the pin FREQREF to become an output and source
a locked clock. The locked clock is the same as DCL clock.
TSEN BCH Enable
When this bit is set to 1, it enables the pin TSEN to operate an off–chip bus driver during the B1 and
B2 timeslots. When the timeslot assigner is enabled, the TSEN signal is active during the timeslot
in which B1 and B2 channel data is transferred.
SFAX/SFAR Enable
When this bit is set to 1, it enables two pins on the MC145572 to be used to control and/or indicate
the location of the transmit and receive superframes relative to the IDL2 interface.
D Channel Port Enable
When this bit is set to 1 and pin MCU/GCI = 1, three pins are enabled on the MC145572 to be used
as a D channel port. When the D channel port is enabled, D channel information transmitted on the
U–interface is taken from DCH in2 , and D channel information from the U–interface is transmitted on
both DCH out and D out2 . (Note that D out does not output the D channel data when the
IDL2 interface is in timeslot mode, and the TSA D Enable is not set to 1.)
4.5.10
OR9: Configuration Register 3
This register is used to control the analog loopback and clocks that are available at MC145572 pins.
After a hardware or software reset, all bits default to 0 to maintain MC145472/MC14LC5472 compat-
ibility.
CAUTION
Reserved bit b7 must be set to 0 at all times.
b7
b6
b5
b4
b3
b2
b1
b0
OR9
Reserved
Open
Analog
CLKOUT
4096
2048
1536
4096
Feedback
Loopback
2048
Hirate
Disable
Disable
Disable
Switches
rw
rw
rw
rw
rw
rw
rw
rw
Open Feedback Switches
When this bit is set to 1, it opens the internal feedback path between the transmit (TxP/TxN) and
the receive (RxP/RxN) sections. This feature may be used in conjunction with analog loopback.
Analog Loopback
When this bit is set to 1, it invokes a receive analog loopback on the MC145572.
CLKOUT 2048
When this bit is set to 1, it enables a 20.48 MHz buffered clock output on pin 25 of the MC145572FN
and on pin 8 of the MC145572PB.
4096 Hirate
When this bit is set to 1, it causes the 4.096 MHz clock output to cleanly transition to a 10.24 MHz
rate. When set back to 0, the clock cleanly transitions to 4.096 MHz.
For More Information On This Product,
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MC145572
MOTOROLA
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