MC145572PB Freescale Semiconductor, MC145572PB Datasheet - Page 127

• Manufacturer Part Number: MC145572PB
• Manufacturer: Freescale Semiconductor

Specifications of MC145572PB

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Not Compliant

MOTOROLA
8.2
8.3
INTERFACE SIGNALS
Seven signal pins are available for the time division multiplex bus interface in GCI mode.
During all other GCI channels, if present, D out is off. D in accepts data during the channel selected
by S0, S1, and S2. During other GCI channels, if present, D in ignores any data that is present.
GCI FRAME STRUCTURE
The GCI interface supports two types of frame formats: the single GCI channel and the multiplexed
GCI channel formats. A single GCI channel has the following subchannels: two B channels, Monitor
channel, ISDN D channel, Command/Indicate channel, and A and E bits. See Figure 8–2.
Referring to Figure 8–2, the two B channels are used to convey customer data between the
MC145572 and other GCI devices. The Monitor channel bits are used to convey register and mainte-
nance information between the MC145572 and other GCI devices. The D bits carry the ISDN basic
access D channel. The Command/Indicate bits are used for activation and deactivation of the
MC145572 and for control functions. The A and E bits are used as handshake signals during the
transfer of monitor channel messages.
A multiplexed GCI frame contains from two to eight GCI frames in each 125 s period. Table 8–2
summarizes the number of GCI frames that can be multiplexed into a 125 s period. Figure 8–3
shows how multiple GCI frames are multiplexed into a 125 s period.
S2, S1, S0 — Used to select the active GCI channel in multiplexed GCI frames.
DCL — 2x data clock.
FSC — The 8 kHz frame synchronization pulse.
D in — The MC145572 reads data from the GCI interface into this pin during the active GCI channel
selected by S2, S1, S0.
D out — In GCI mode, this pin is an open drain output and must be pulled to V DD through a resistor.
The MC145572 outputs data to the GCI interface from this pin during the active GCI channel
selected by S2, S1, S0.
Freescale Semiconductor, Inc.
For More Information On This Product,
GCI Master
GCI Master
GCI Slave
GCI Slave
Table 8–2. Multiplexed GCI Frame Configuration
Mode
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Table 8–1. GCI Master Mode Clock
Clock Rate
2.048 MHz
512 kHz
MC145572
2.048 MHz
4.096 MHz
512 kHz
512 kHz
Clock
Rate Selection
Maximum GCI Frames
CLKSEL
0
1
in Multiplex
1
4
1
8
8–3