MC145572PB Freescale Semiconductor, MC145572PB Datasheet - Page 130

• Manufacturer Part Number: MC145572PB
• Manufacturer: Freescale Semiconductor

Specifications of MC145572PB

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Not Compliant

8–6
8.3.2.1
8.3.1
8.3.2
Monitor Channel Operation
The Monitor channel is used to access the internal registers of the MC145572 in order to support
U–interface maintenance channel operations. All Monitor channel messages are two bytes in length.
Each byte is sent twice to permit the receiving GCI device to verify data integrity. In ISDN applications,
the Monitor channel is used for access to the U–interface maintenance messages.
The A and E bits in the GCI channel are used to control and acknowledge Monitor channel transfers
between the MC145572 and another GCI device. When the Monitor channel is inactive, the A and
the E bit times from D out are both high impedance. The A and E bits are active when they are driven
to V SS during their respective bit times. Pull-up resistors are required on D in and D out . The E bit
indicates the transmission of a new Monitor channel byte. The A bit from the opposite direction is
used to acknowledge the Monitor channel byte transfer.
An idle Monitor channel is indicated by both A and E bits being inactive for two GCI frames. The A
and E bits are high impedance when inactive. The Monitor channel data is $FF.
The originating GCI device transmits a byte onto the Monitor channel after receiving the A and E bits
equal to 1 for at least two consecutive GCI frames. The originating GCI device also sets its outgoing
E bit to 0 in the same GCI frame as the byte that is transmitted. The transmitted byte is repeated
for at least two GCI frames, or is repeated in subsequent GCI frames, until the MC145572 acknowl-
edges receiving two consecutive GCI frames containing the same byte.
Once the MC145572 acknowledges the first byte, the sending device sets E to high impedance and
transmits the first frame of the second byte. Then, the second byte is repeated with the E bit low until
it is acknowledged. See Figures 8–4 through 8–8 for details of Monitor channel procedure.
The destination GCI device verifies that it has received the first byte by setting the A bit to 0 towards
the originating GCI device for at least two GCI frames. Successive bytes are acknowledged by the
receiving device setting A to high impedance on the first instance of the next byte, followed by A being
cleared to 0 when the second instance of the byte is received.
The entire register set of the MC145572 can be accessed via the Monitor channel. All M4 channel
activity is automatically handled by the MC145572 when configured for GCI mode. The MC145572
issues Monitor channel messages whenever the received eoc, M4, or M5/M6 messages received
from the U–interface change, and appropriate dual–checking or trinal–checking of bits has been
done. In normal GCI operation it is not necessary to read or write the internal registers of the
MC145572.
If the receiving GCI device does not receive the same Monitor channel byte in two consecutive GCI
frames, it indicates this by leaving A = 0 until two consecutive identical bytes are received. The last
byte of the sequence is indicated by the originating GCI device setting its E bit to a 1 for two succes-
sive GCI frames. Figure 8–5 shows an example of an delayed GCI Monitor channel message.
Monitor Channel Messages and Commands
The MC145572 supports three basic types of Monitor channel messages. The first group of mes-
sages are commands that read or write the internal register set of the MC145572. See Chapter 4
for a complete description of the MC145572 register set. The second group of messages are
responses from the MC145572. These responses are transmitted by the MC145572 after it receives
a register read or write command over the Monitor channel. The third group of Monitor channel mes-
sages are interrupt indication messages. These are transmitted by the MC145572 whenever a
change is detected in the Maintenance Channel Receive registers BR1, BR3, or R6.
MONITOR CHANNEL COMMANDS
A GCI device transmits Monitor channel commands to a receiving MC145572 to gain access to its
internal register set. The receiving MC145572 then transmits a Monitor channel response message
onto the Monitor channel for commands that request data to be read from an internal register. Com-
mands that write data to an internal MC145572 register are accepted and acted upon, but the
MC145572 does not issue a response message. Monitor channel commands are given in Table 8–3.
The MC145572 acknowledges all messages it receives over the Monitor channel. If an invalid mes-
sage is received, the MC145572 acknowledges it, but does not take any action.
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MC145572
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